IBIS: History and Future Direction

IBIS History and Future Direction

Bob Ross, Past Chair of the EIA IBIS Open Forum, June 3, 2002

The IBIS format is now a widely supported modeling format used by semiconductor manufacturers and EDA products, including several SPICE simulators. Many concerns expressed in Dr. Johnson's earlier article on IBIS have been addressed. Solutions to others are being considered .

IBIS is thriving not because it is always the best format, but because it provides the right balance between comprehensive detail, sufficient accuracy, and model availability. Users support IBIS because it gives fast, reliable, and accurate board-level simulation results. Semiconductor manufacturers support IBIS because it specifies device behavior without revealing proprietary device process and architectural information. The industrial infrastructure, driven by common needs, has enabled IBIS acceptance with freeware and commercial utilities. It has opened the pipeline for models developed by simulation and measurement.

IBIS models are available from at least three sources:

  1. Many semiconductor manufacturers provide free, downloadable IBIS models, and others provide them through direct contact.
  2. Commercial vendors, including prominent EDA vendors , are providing IBIS libraries and modeling services.
  3. Users are also developing IBIS models and utilities, and managing internal IBIS libraries.

Since its beginnings in 1993, IBIS has evolved, keeping up with advances in digital circuitry and simulation needs. IBIS has been applied in higher speed applications than originally thought possible. Work continues on further enhancements and new directions.

13.5.1 IBIS Historical Overview

In the early 1990s, Intel Corporation initiated a spreadsheet, table-based model to convey the requirements of PCI bus drivers and provide a format among different divisions for external communication. Several vendor-specific formats did exist at that time, making data preparation and model availability primary issues. Intel invited EDA vendors to help define a common model format for industry. As a result of this collaboration, IBIS Version 1.0 was issued in June 1993 in an ASCII text “based model format, and a clarification update Version 1.1 was introduced in August 1993. The group formed the IBIS Open Forum to keep up with technical needs and promote the availability of IBIS models. IBIS Version 1.1 provided the initial framework with the understanding that it would be expanded in an upward compatible manner. The IBIS Open Forum issued an official syntax checker and electronic parser known as ibis_chk. North Carolina State University (NCSU) started work on a SPICE-to-IBIS model generation utility designated as s2ibis. These utilities along with a cookbook and public IBIS Open Forum support helped seed the industry to produce IBIS models.

More EDA vendors, semiconductor manufacturers, and users joined the Forum, and through cooperative efforts IBIS Version 2.0 was presented in June 1994 with many practical extensions. In February 1995 the Forum became affiliated with the ( renamed to) Electronic Industries Alliance (EIA) as the EIA IBIS Open Forum. With formal review and letter ballot processes, IBIS Version 2.1 was issued and approved in December 1995 by the American National Standards Institute (ANSI) as ANSI/EIA-656. IBIS Version 2.1 provided a rich baseline set of features suitable for accurately modeling most digital buffers for many years . The EIA IBIS Open Forum upgraded the syntax checker and parser to ibischk2, and NCSU produced a corresponding s2ibis2 utility.

The EIA IBIS Open Forum continued making additions and improvements that led to the adoption of IBIS Version 3.2 nationally as ANSI/EIA-656-A by ANSI in September 1999 and internationally as IEC 62014-1 in April 2001 by the International Electrotechnical Commission (IEC). IBIS Version 3.2 included formats for advanced electronic features in some popular devices. It also provided extended package model features and electrical board descriptions. A corresponding ibischk3 was issued. Private and commercial utilities and services emerged for IBIS model development.

13.5.2 Comparison to SPICE

Like SPICE models, IBIS models are formatted in human-readable ASCII text. However, IBIS models do not require manufacturers to disclose proprietary information about how their circuits are designed. The critical electrical characteristics are described in IBIS by a purely behavioral model. Some manufacturers view this as a distinct advantage. IBIS models leave room for a chip manufacturer to create new implementations and process variations that still fit within the parameters of the published IBIS model (and are still therefore guaranteed to work in a user 's circuit). That's a significant point in favor of IBIS. Lastly, SPICE models tend to be buffer-centric ”the model often represents only one of several inputs or outputs on a component. IBIS models are component-centric ”the model describes all the pins of a physical component. EDA vendors like IBIS because it integrates complete electrical component descriptions with the preexisting physical data already used to describe the thousands of connections in a large design. As a result, models of current devices are now becoming more readily available in IBIS than in SPICE formats.

13.5.3 Future Directions

Many people have contributed to the evolution of IBIS. From the very beginning, certain format inconsistencies and even a few mistakes have been introduced. Shorter- term practical commercial reality drove the evolution more than did technical purity. However, the existing format is capable of serving industry for many years. New IBIS versions may appear, focusing less on technical advances and more on informational and datasheet content. In fact, the future directions are to link IBIS with other simulator formats, pursue related technical areas, and promote better models. The EIA IBIS Open Forum has been directly and indirectly involved with groups doing the following:

  • Developing a multilingual extension format to support technical extensions and other features within a co-simulation environment with other languages.
  • Advancing an interconnect format for both package and connector modeling improvements.
  • Using IBIS within the Integrated Circuits Electromagnetic Model (ICEM) pending IEC standard for core noise generation.
  • Tracking frequency-domain modeling details to provide better resonance detection.
  • Improving IBIS models by forming a Quality Working Group to work on checklists and other support material.

The EIA IBIS Open Forum has investigated how to quickly add new technical features. It originally considered developing a new macro language for configuring buffer models. However, it is now considering leveraging off of established languages such as SPICE, VHDL-AMS, and Verilog-AMS in a co-simulation setting where needed. SPICE features can be used for advanced buffer detail and internal die interconnections. The analog and mixed-signal (AMS) extensions open the door to new capability with equation-based models and integration with logic design. Complex IBIS elements can be created using smaller IBIS building blocks and logic controls. IBIS can be the model container for analog circuits such as regulators, timers, operational amplifiers , et cetera, and for digital logic blocks. The multilingual approach will allow IBIS to enable solutions for SSO analysis, buffer interaction on internal die-level timing, and EMI core noise modeling. New buffer features can be implemented quickly within existing executable code.

No one can really predict how IBIS will evolve . IBIS might even be discarded and replaced with a new way of modeling. However, IBIS more likely will continue to advance in the broadest sense based on commercial interests and driven by individuals facing increasingly difficult challenges.


Transmission Line Parameters

Performance Regions

Frequency-Domain Modeling

Pcb (printed-circuit board) Traces

Differential Signaling

Generic Building-Cabling Standards

100-Ohm Balanced Twisted-Pair Cabling

150-Ohm STP-A Cabling

Coaxial Cabling

Fiber-Optic Cabling

Clock Distribution

Time-Domain Simulation Tools and Methods

Points to Remember

Appendix A. Building a Signal Integrity Department

Appendix B. Calculation of Loss Slope

Appendix C. Two-Port Analysis

Appendix D. Accuracy of Pi Model

Appendix E. erf( )


High-Speed Signal Propagation[c] Advanced Black Magic
High-Speed Signal Propagation[c] Advanced Black Magic
ISBN: 013084408X
Year: 2005
Pages: 163

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