Pcb traces are used for extremely high-frequency connections within a single pcb and on backplanes connecting one or more pcbs. Figure 5.1 illustrates the microstrip, embedded microstrip, centered stripline, offset stripline , and coplanar waveguide structures as commonly employed in digital products.

Figure 5.1. Digital products employ a rich variety of pcb transmission-line structures.

The microstrip trace has a solid reference plane on only one side. The stripline lies between two solid reference planes. A coplanar waveguide has grounded metal on either side of the trace, with or without a solid reference layer underneath.

Analysis of pcb performance generally relies on three assumptions about the pcb-trace geometry.

**There exist well-defined uniform paths for the flow of both signal current and returning signal current.**- The conductors are long compared to the spacing between the signal and return paths.
- The conductors are shorter than the critical RC length l RC (see [3.56] in Section 3.5.1, "Boundary of RC Region").

Conditions 1 and 2 make possible the use of the telegrapher's equations. In high-speed digital designs these conditions generally imply the existence of a solid conducting reference plane underlying the signal conductors, although it is also possible to satisfy the conditions using a differential pair routed without a reference plane.

In the absence of a well-defined return-current path ”for example, in a two-layer pcb that may incorporate a grid of power and ground tracks instead of a solid reference plane ”one is relegated to analyzing each circuit as a large lumped-element structure (or a series of lumped-element structures) with randomized values of inductance and capacitance . In this situation the performance of individual traces at high speeds will be highly variable. Terminations may improve performance, but will not be a reliable means of controlling ringing, as the trace performance will change every time the trace is moved in successive layout passes .

Solid reference planes, if adjusted to the correct distance from each trace layer, endow all traces with a uniform impedance regardless of their routing, making possible the use of terminations as a reliable strategy for controlling ringing. Solid planes also have the side benefit of greatly reducing crosstalk between signals.

Condition 3 ensures that the total DC resistance of the trace remains a small fraction of the characteristic impedance. A trace under this condition never exhibits any noticeable RC behavior. It transitions directly from the lumped-element region (which applies at low frequencies) to the LC region (at higher frequencies) without passing through the RC region. Such traces have a fairly constant value of characteristic impedance at all frequencies above the lumped-element region, a property which simplifies the analysis. Figure 3.2 illustrates the critical RC length for a typical 50- W pcb trace of 150- m m (5.9-mil) width at about 2 meters (78 in.). [37] Analysis of longer traces must take into account the varying nature of characteristic impedance and attenuation in the RC region.

[37] The critical RC length is that length at which the outer boundary of the lumped-element region intersects the left edge of the LC region.

On-chip interconnections do not meet condition 3. They suffer from very high resistance in the metallization layer, due to the use of extremely thin metallic plating , and even higher resistance in the poly layers . As a result, most on-chip interconnections do in fact operate in the RC region.

When analyzing pcb traces shorter than 25 cm (10 in.) operating at edge rates no faster than 500 ps (1 GHz bandwidth), you can generally ignore trace losses. They just aren't significant enough to worry about. On longer traces or at higher speeds, the skin and dielectric losses can become quite significant.

POINT TO REMEMBER

- Analysis of pcb performance generally assumes:
Well-defined uniform paths for both signal current and returning signal current.

Conductors long compared to the spacing between the signal and return paths.

Conductors shorter than the critical RC length l RC .

Fundamentals

- Impedance of Linear, Time-Invariant, Lumped-Element Circuits
- Power Ratios
- Rules of Scaling
- The Concept of Resonance
- Extra for Experts: Maximal Linear System Response to a Digital Input

Transmission Line Parameters

- Transmission Line Parameters
- Telegraphers Equations
- Derivation of Telegraphers Equations
- Ideal Transmission Line
- DC Resistance
- DC Conductance
- Skin Effect
- Skin-Effect Inductance
- Modeling Internal Impedance
- Concentric-Ring Skin-Effect Model
- Proximity Effect
- Surface Roughness
- Dielectric Effects
- Impedance in Series with the Return Path
- Slow-Wave Mode On-Chip

Performance Regions

- Performance Regions
- Signal Propagation Model
- Hierarchy of Regions
- Necessary Mathematics: Input Impedance and Transfer Function
- Lumped-Element Region
- RC Region
- LC Region (Constant-Loss Region)
- Skin-Effect Region
- Dielectric Loss Region
- Waveguide Dispersion Region
- Summary of Breakpoints Between Regions
- Equivalence Principle for Transmission Media
- Scaling Copper Transmission Media
- Scaling Multimode Fiber-Optic Cables
- Linear Equalization: Long Backplane Trace Example
- Adaptive Equalization: Accelerant Networks Transceiver

Frequency-Domain Modeling

- Frequency-Domain Modeling
- Going Nonlinear
- Approximations to the Fourier Transform
- Discrete Time Mapping
- Other Limitations of the FFT
- Normalizing the Output of an FFT Routine
- Useful Fourier Transform-Pairs
- Effect of Inadequate Sampling Rate
- Implementation of Frequency-Domain Simulation
- Embellishments
- Checking the Output of Your FFT Routine

Pcb (printed-circuit board) Traces

- Pcb (printed-circuit board) Traces
- Pcb Signal Propagation
- Limits to Attainable Distance
- Pcb Noise and Interference
- Pcb Connectors
- Modeling Vias
- The Future of On-Chip Interconnections

Differential Signaling

- Differential Signaling
- Single-Ended Circuits
- Two-Wire Circuits
- Differential Signaling
- Differential and Common-Mode Voltages and Currents
- Differential and Common-Mode Velocity
- Common-Mode Balance
- Common-Mode Range
- Differential to Common-Mode Conversion
- Differential Impedance
- Pcb Configurations
- Pcb Applications
- Intercabinet Applications
- LVDS Signaling

Generic Building-Cabling Standards

- Generic Building-Cabling Standards
- Generic Cabling Architecture
- SNR Budgeting
- Glossary of Cabling Terms
- Preferred Cable Combinations
- FAQ: Building-Cabling Practices
- Crossover Wiring
- Plenum-Rated Cables
- Laying Cables in an Uncooled Attic Space
- FAQ: Older Cable Types

100-Ohm Balanced Twisted-Pair Cabling

- 100-Ohm Balanced Twisted-Pair Cabling
- UTP Signal Propagation
- UTP Transmission Example: 10BASE-T
- UTP Noise and Interference
- UTP Connectors
- Issues with Screening
- Category-3 UTP at Elevated Temperature

150-Ohm STP-A Cabling

- 150-Ohm STP-A Cabling
- 150- W STP-A Signal Propagation
- 150- W STP-A Noise and Interference
- 150- W STP-A: Skew
- 150- W STP-A: Radiation and Safety
- 150- W STP-A: Comparison with UTP
- 150- W STP-A Connectors

Coaxial Cabling

- Coaxial Cabling
- Coaxial Signal Propagation
- Coaxial Cable Noise and Interference
- Coaxial Cable Connectors

Fiber-Optic Cabling

- Fiber-Optic Cabling
- Making Glass Fiber
- Finished Core Specifications
- Cabling the Fiber
- Wavelengths of Operation
- Multimode Glass Fiber-Optic Cabling
- Single-Mode Fiber-Optic Cabling

Clock Distribution

- Clock Distribution
- Extra Fries, Please
- Arithmetic of Clock Skew
- Clock Repeaters
- Stripline vs. Microstrip Delay
- Importance of Terminating Clock Lines
- Effect of Clock Receiver Thresholds
- Effect of Split Termination
- Intentional Delay Adjustments
- Driving Multiple Loads with Source Termination
- Daisy-Chain Clock Distribution
- The Jitters
- Power Supply Filtering for Clock Sources, Repeaters, and PLL Circuits
- Intentional Clock Modulation
- Reduced-Voltage Signaling
- Controlling Crosstalk on Clock Lines
- Reducing Emissions

Time-Domain Simulation Tools and Methods

- Ringing in a New Era
- Signal Integrity Simulation Process
- The Underlying Simulation Engine
- IBIS (I/O Buffer Information Specification)
- IBIS: History and Future Direction
- IBIS: Issues with Interpolation
- IBIS: Issues with SSO Noise
- Nature of EMC Work
- Power and Ground Resonance

Points to Remember

Appendix A. Building a Signal Integrity Department

Appendix B. Calculation of Loss Slope

Appendix C. Two-Port Analysis

- Appendix C. Two-Port Analysis
- Simple Cases Involving Transmission Lines
- Fully Configured Transmission Line
- Complicated Configurations

Appendix D. Accuracy of Pi Model

Appendix E. erf( )

Notes

High-Speed Signal Propagation[c] Advanced Black Magic

ISBN: 013084408X

EAN: N/A

EAN: N/A

Year: 2005

Pages: 163

Pages: 163

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