## Article first published in EDN Magazine , January 7, 1999Have you ever had one of those days when nothing seems to go right? My friend Bill Turner and I were debugging a high-speed, heavily pipelined, multiple-clock-phase hardware project one morning when we suddenly realized it would never work. The timing budget didn't add up. We were missing about 2 nsec of setup time at a key latch in the middle of the design. At lunch , over burgers and fries, we put our heads together to find a solution. I marked out a crude timing chart on my place mat, with vertical lines representing the various clock phases. We then nibbled our french fries down to appropriate lengths and placed them horizontally on the chart to represent the setup-and-hold requirements around each clock edge. More french fries showed the minimum and maximum propagation delays out of each latch and through the surrounding logic. A blob of ketchup highlighted the main timing violation. When we finished, we had an accurate (and tasty) representation of the timing constraints for the whole system. A specific, predictable clock skew, applied at a few crucial nodes, can optimize the overall timing budget. Next, we started sliding the french fries back and forth, adjusting the timing of each clock phase, seeking a combination of adjustments that would make the system function. We found that when phase 2 moved to the right about 1 in., it caused all of the other french fries to line up, and the system looked pretty solid. I made a drawing of this final configuration to take back to the office, and we ate the rest of the chart. Timing adjustments like this one occur frequently in high-speed products. Designers often discover that a specific, predictable clock skew, applied at a few crucial nodes, can optimize the overall timing budget, increasing the maximum potential system-operating rate. Until recently, designers implemented intentional clock skew with either fixed-length physical transmission-line delay structures or lumped-element RC delay circuits. Pure semiconductor chain-of-gates delay approaches are unpopular for fixed delays because it's just impossible to produce MOSFET delays with sufficient accuracy. You can make a nice, electronically adjustable MOSFET delay pretty easily, but not an accurate fixed delay ”at least, not if you are trying to produce a general-purpose delay line. For the intentional clock-skew application, however, the situation changes. What's different about a clock signal is that you may use a phase detector to accurately measure the delay of one clock signal relative to another. For example, imagine a simple clock buffer with an electronically adjustable delay (see Figure 12.4). The clock buffer has IN, OUT, and control-adjustment (CNTL) terminals. Using a phase detector, measure the delay of OUT relative to IN. If the phase detector says the output is ahead of schedule, feed that signal back into the adjustment circuit to slow the output. When the output is a little behind, speed it up. Working in this manner, you can program the feedback circuit to obtain any arbitrary output phase to within the tolerance limits of the phase detector. Figure 12.4. This clock buffer architecture uses a phase detector to precisely control delay This architecture resembles a PLL. The basic feedback idea, combined with various internal ring-oscillator and divider-chain circuits, can produce a flexible array of precise output clock phases. A number of vendors now offer clock repeater chips with just this sort of circuitry built in. The repeaters provide varying degrees of individual adjustability in the output clock phases. Just to mention a few, there are the Cypress RoboClock, the Quality Semiconductor TurboClock, and the AMCC S4402. You can use each to produce arbitrary, precise, intentional clock skew where and when you need it. In the high-speed world, timing is everything, so I predict these types of components will be really hot. If you think these parts could help your design, place your order now and ask for a basket of fries to go with them. |

POINT TO REMEMBER

- DLL or PLL technology can produce arbitrary, precise, intentional clock skew where and when you need it.

Fundamentals

- Impedance of Linear, Time-Invariant, Lumped-Element Circuits
- Power Ratios
- Rules of Scaling
- The Concept of Resonance
- Extra for Experts: Maximal Linear System Response to a Digital Input

Transmission Line Parameters

- Transmission Line Parameters
- Telegraphers Equations
- Derivation of Telegraphers Equations
- Ideal Transmission Line
- DC Resistance
- DC Conductance
- Skin Effect
- Skin-Effect Inductance
- Modeling Internal Impedance
- Concentric-Ring Skin-Effect Model
- Proximity Effect
- Surface Roughness
- Dielectric Effects
- Impedance in Series with the Return Path
- Slow-Wave Mode On-Chip

Performance Regions

- Performance Regions
- Signal Propagation Model
- Hierarchy of Regions
- Necessary Mathematics: Input Impedance and Transfer Function
- Lumped-Element Region
- RC Region
- LC Region (Constant-Loss Region)
- Skin-Effect Region
- Dielectric Loss Region
- Waveguide Dispersion Region
- Summary of Breakpoints Between Regions
- Equivalence Principle for Transmission Media
- Scaling Copper Transmission Media
- Scaling Multimode Fiber-Optic Cables
- Linear Equalization: Long Backplane Trace Example
- Adaptive Equalization: Accelerant Networks Transceiver

Frequency-Domain Modeling

- Frequency-Domain Modeling
- Going Nonlinear
- Approximations to the Fourier Transform
- Discrete Time Mapping
- Other Limitations of the FFT
- Normalizing the Output of an FFT Routine
- Useful Fourier Transform-Pairs
- Effect of Inadequate Sampling Rate
- Implementation of Frequency-Domain Simulation
- Embellishments
- Checking the Output of Your FFT Routine

Pcb (printed-circuit board) Traces

- Pcb (printed-circuit board) Traces
- Pcb Signal Propagation
- Limits to Attainable Distance
- Pcb Noise and Interference
- Pcb Connectors
- Modeling Vias
- The Future of On-Chip Interconnections

Differential Signaling

- Differential Signaling
- Single-Ended Circuits
- Two-Wire Circuits
- Differential Signaling
- Differential and Common-Mode Voltages and Currents
- Differential and Common-Mode Velocity
- Common-Mode Balance
- Common-Mode Range
- Differential to Common-Mode Conversion
- Differential Impedance
- Pcb Configurations
- Pcb Applications
- Intercabinet Applications
- LVDS Signaling

Generic Building-Cabling Standards

- Generic Building-Cabling Standards
- Generic Cabling Architecture
- SNR Budgeting
- Glossary of Cabling Terms
- Preferred Cable Combinations
- FAQ: Building-Cabling Practices
- Crossover Wiring
- Plenum-Rated Cables
- Laying Cables in an Uncooled Attic Space
- FAQ: Older Cable Types

100-Ohm Balanced Twisted-Pair Cabling

- 100-Ohm Balanced Twisted-Pair Cabling
- UTP Signal Propagation
- UTP Transmission Example: 10BASE-T
- UTP Noise and Interference
- UTP Connectors
- Issues with Screening
- Category-3 UTP at Elevated Temperature

150-Ohm STP-A Cabling

- 150-Ohm STP-A Cabling
- 150- W STP-A Signal Propagation
- 150- W STP-A Noise and Interference
- 150- W STP-A: Skew
- 150- W STP-A: Radiation and Safety
- 150- W STP-A: Comparison with UTP
- 150- W STP-A Connectors

Coaxial Cabling

- Coaxial Cabling
- Coaxial Signal Propagation
- Coaxial Cable Noise and Interference
- Coaxial Cable Connectors

Fiber-Optic Cabling

- Fiber-Optic Cabling
- Making Glass Fiber
- Finished Core Specifications
- Cabling the Fiber
- Wavelengths of Operation
- Multimode Glass Fiber-Optic Cabling
- Single-Mode Fiber-Optic Cabling

Clock Distribution

- Clock Distribution
- Extra Fries, Please
- Arithmetic of Clock Skew
- Clock Repeaters
- Stripline vs. Microstrip Delay
- Importance of Terminating Clock Lines
- Effect of Clock Receiver Thresholds
- Effect of Split Termination
- Intentional Delay Adjustments
- Driving Multiple Loads with Source Termination
- Daisy-Chain Clock Distribution
- The Jitters
- Power Supply Filtering for Clock Sources, Repeaters, and PLL Circuits
- Intentional Clock Modulation
- Reduced-Voltage Signaling
- Controlling Crosstalk on Clock Lines
- Reducing Emissions

Time-Domain Simulation Tools and Methods

- Ringing in a New Era
- Signal Integrity Simulation Process
- The Underlying Simulation Engine
- IBIS (I/O Buffer Information Specification)
- IBIS: History and Future Direction
- IBIS: Issues with Interpolation
- IBIS: Issues with SSO Noise
- Nature of EMC Work
- Power and Ground Resonance

Points to Remember

Appendix A. Building a Signal Integrity Department

Appendix B. Calculation of Loss Slope

Appendix C. Two-Port Analysis

- Appendix C. Two-Port Analysis
- Simple Cases Involving Transmission Lines
- Fully Configured Transmission Line
- Complicated Configurations

Appendix D. Accuracy of Pi Model

Appendix E. erf( )

Notes

High-Speed Signal Propagation[c] Advanced Black Magic

ISBN: 013084408X

EAN: N/A

EAN: N/A

Year: 2005

Pages: 163

Pages: 163

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