Article first published in EDN Magazine , August 3, 1998
An ideal digital clock, from the standpoint of system timing, is an infinite succession of very fast-edged, identical pulses with a perfectly repeating structure. Unfortunately, from an electromagnetic compatibility (EMC) perspective, such a clock is also the worst of all possible signals. It radiates like crazy. This situation is calmly referred to in polite engineering circles as a fundamental tradeoff . Late at night, when we engineers let our hair down, I've heard other terms used to describe it.
The problem with a simple, repetitive signal like a clock is that all its power can become concentrated at a relatively small number of discrete frequencies. When these discrete frequencies leak out of your product's packaging into the outside world, all the radiated clock power is concentrated in a small number of radiated modes.
Clock modulation of any kind complicates the attachment of your product to any form of truly synchronous logic.
Data signals don't do this. Random data signals spread their power among a much larger number of radiated modes, each with a smaller average power. That's better, because both FCC and EN emissions regulations are written to penalize the worst-case (peak) radiation in any given mode.
Although the data nets in your product undoubtedly radiate more total power than do the clocks, the data nets usually contribute less to the FCC/EN peak radiation measurements, because the radiation from the data nets is spread evenly at a relatively low level across the vast territory of the electromagnetic spectrum.
Over the years , various techniques have been proposed for modulating, or dithering, the clock frequency in order to break up the accumulated power into a larger number of new modes, each with a reduced power content. If the new modes are separated from each other by more than 100 KHz, which is the effective bandwidth used for FCC/EN spectral power density measurements, the peak power measured within each 100 KHz band will be reduced. Such proposals are backed by solid theoretical reasoning and, for the most part, they are technically sound. Modulating the clock really does reduce the peak measured radiation. Unfortunately, the practical realization of this technique comes at a very high cost. A proper appreciation of the architectural cost of a modulated clock may be gained by considering the many uses to which a clock may be put.
First and foremost, the clock directs the synchronous neural firings of your product's digital brain. When working with a purely digital product architecture, you might conclude that you need merely to guarantee a minimum clock period. Any modulation or dither above and beyond the minimum period should, theoretically, have no impact on the correctness of the computed results. Dither may perturb the timing of the final result (it will always be slower than if you had run the machine continuously at full speed), but it should not affect the correctness ”at least that's the theory.
The practical side of the matter is that intentional clock modulation of any kind complicates the attachment of your product to any form of truly synchronous logic. For example, a modulated clock can never be used as the reference clock input to any advanced data communication transceiver (Ethernet, Fibre Channel, FDDI, ATM, SONET, or ADSL). These parts require a pristine, jitter-free reference clock. When connected to a jittery clock, these transceivers may fail to lock or may lock poorly, leading to data errors or other flaky behavior. Never use an intentionally modulated clock as the reference input for any kind of data communication transceiver.
For similar reasons, you'll find a modulated clock unsuitable as a main system clock for any modern high-performance CPU. These parts all contain internal clock multiplier circuits (PLLs) which are very sensitive to jitter in the reference clock. The Semiconductor Industry Association roadmap  implies that more and more components will incorporate clock multipliers in future years. This is a trend you won't want to forgo.
Finally, in case you are not yet convinced, I'd like to point out that wireless communication is becoming progressively more important in many applications. Modulated clocks should not be used as a reference source for RF-communication systems. Especially for direct-sequence spread spectrum links, where the data rate and the communications modulation rate (the chip rate) are related in a fixed manner, it is important to have a stable, jitter-free system clock for the transfer of data to and from the RF subsystem.
In each of the three cases I've outlined here, it is of course still possible to connect a jittery clock domain to a purely synchronous subsystem. The connection requires a clean reference clock for the synchronous side of your product (in addition to the jittery modulated clock you already have), plus a dual-ported asynchronous FIFO to connect the jittery clock domain to the purely synchronous domain. Why bother with this sort of architecture?
In this author's opinion, if control of EMC is your objective, you will be better served by any combination of the following techniques:
Any of these techniques will deliver the clock you need at a cost you can afford.
Postscript September 3, 2002 ”Some CPU manufacturers now make PLL-based clock multipliers that tolerate specific amounts of intentional clock modulation, but I still think it's a bad idea.
12.13.1 Signal Integrity Mailbag
Article first published in EDN Magazine , October 8, 1998
My article "Intentional Clock Modulation" spurred some interesting responses from readers. Here are some of the best.
Kevin Slattery, Chrysler Electronics: I couldn't agree more with your recent article in EDN concerning clock dithering. I work in the EMC department for Chrysler Electronics. Our EMI requirements are quite stringent (FCC would be a cakewalk ). What with the stringent requirements and the automotive industry's aversion to spending money of any kind, we have tried many of the more esoteric solutions, such as clock dithering. The major problem with dithering the clock is just as you said: Most CPUs that we use employ a PLL for generating the internal CPU clock. Modulating the reference just makes everything worse . It is a nice idea for a very small subset of EMI problems....
Eric V. Berger, NASA: Your August 3 EDN article about clock modulation was very refreshing. When I first heard about this practice, I was appalled. The radiated energy is not reduced, just the peaks in the frequency domain are. This is like getting rid of a cow pie by stomping on it. Perhaps the regulations will be changed to stop this practice.
Dave Cuthbert, Micron Technology: I liked your article on clock modulation. I don't like intentional jitter either, but it does have its uses. In the case of PCs it is a very low-cost way of achieving EMC compliance without the cost of other solutions. But does meeting EMC compliance this way meet the letter of the law but violate the intent of these laws? In regards to narrowband communication, a spread spectrum clock may be alright. But what about wideband signals such as analog television?
Doug Butler, Imetrix: The one important point about clock modulation that many engineers may not realize is that it does nothing to reduce the actual interference that customers will see in the field! It is a clever scheme to circumvent FCC regulations and nothing more. If one milliwatt of energy at exactly 60 MHz will cause a certain amount of disruption to an audio pre-amp, smearing that same energy from 59 MHz to 61 MHZ will cause almost exactly the same disruption. The only legitimate solution is to reduce the energy radiated or shift it in frequency by a very large amount, like at least a factor of two or three.
FCC regulations are not obstacles to be overcome . They are tools to help us solve real problems.
The FCC regulations are not obstacles to be overcome. They are tools to help us solve real problems. When finding ways to comply with the rules, we need to realize that rules are there to prevent problems, and simply complying to the exact letter of the rules may still leave the problems unsolved. The FCC rules sometimes need some commonsense interpretation. Unless we designers use our common sense, the FCC will have to rewrite the rules to eliminate loopholes like clock dithering, which will make the rules more complicated and restrictive than they currently are.
Dan Nitzan, Network Video Technologies: Another way for clock modulation to assist in passing open -field emissions testing is to modulate the clock with some audio program source. That way, when the emissions technician comes across your nasty peak, he or she will pass right by, thinking it's some local radio station....
Martin Graham, University of California, Berkeley: Yet another way to pass the test is to park an unmarked white van next to the FCC open-field site. Have the van emit high levels of AM-modulated interference right on top of your clock frequency, masking the clocks.
POINT TO REMEMBER
12.13.2 Jitter-Free Clocks
Article first published in EDN Magazine , August 5, 1999
Three things I've always wanted in a clock repeater: zero delay, zero jitter, and zero emissions. This combination of features would be absolutely ideal for large-system clock distribution. The first semiconductor vendor that produces such a component will be looking at a lucrative market.
The problem is, conventional wisdom says that you can have any two of my ideal features, but not all three.
For example, today I can buy a so-called zero-delay clock repeater . Such a part incorporates PLL technology. The part has one reference clock input and multiple buffered clock outputs. The internal PLL continuously monitors the relation between the phase of the input reference clock and the phase of the outputs. The PLL then adjusts the output transitions so they land precisely on top of the input transitions within a tight timing window ”perhaps as small as 100 psec. The input-to-output delay is, effectively, zero. With sufficient power supply filtering, the zero-delay part can also produce very low jitter.
Scrambled clocks significantly improve radiated emissions without adding jitter.
What this part does not do is generate zero emissions. The continuous, harmonic structure of the clock creates huge peaks in the emission spectrum (at multiples of the clock frequency) ”the kind of huge peaks that keep EMC engineers awake at night.
How about using a spread-spectrum clock? As defined in the current literature, a spread-spectrum clock is frequency-modulated so that its center frequency undulates back and forth around a nominal value. The intentional jitter, or frequency wander, in a spread-spectrum clock tends to smear the spectral peaks. The resulting spectrum has peaks in the same positions , but they are broader and lower. In the limit with extreme amounts of frequency smearing, the peaks almost disappear. The spread-spectrum idea gets you the zero-emissions property but blows it on jitter. You cannot easily interface a spread-spectrum clock to any normal communications device that requires a steady, jitter-free frequency reference. This deficiency, in my opinion, limits the applicability of spread-spectrum clocking.
Is there any way to make a timing reference that has low jitter and low spectral peaks and at the same time is compatible with zero-delay-repeater structures? Yes. One solution to this problem is a well-established, mature technology in current production. Engineers just haven't applied this technology to the clock timing problem on pcbs.
The solution is a scrambled clock (Figure 12.64). That is, a digital signal with transitions at fixed integral points in time, but with random high or low transitions at each point. Think of it like a serial data communications signal with pseudorandom data. The PLL circuit you need to recover the clock from a pseudorandom data stream is not that much different from the PLL circuit in an ordinary zero-delay clock repeater. If you have already concluded that the zero-delay repeater is a good thing, then the extra circuitry that a zero-delay scrambled repeater requires is trivial.
Figure 12.64. A zero-delay PLL structure works basically the same way with either a regular clock or a scrambled clock.
Scrambling smears the spectrum much like spread-spectrum frequency modulation, but with one key difference: The clock edges remain fixed in precisely quantized positions. Therefore, jitter on the recovered clock is very low.
A pseudorandom sequence only 256 bits long breaks up the clock spectrum into 256 individual peaks, each of which carries approximately 1/256 of the full clock energy, for a peak-power reduction of better than 20 dB.
Let me point out a few other tricks you'll want to use if you start working with scrambled clocks. First, you will want to standardize the pseudorandom clock sequence so it is predictable. This step simplifies the design of the PLL recovery circuit. Second, given a sequence with exactly N transitions, you can use a simple divide-by- N counter to produce a frequency reference precisely locked to the incoming clock rate. On power-up , this reference jump-starts the PLL. Such an "acquisition aid" significantly reduces the lock-up time. Finally, you want a sequence with a high rate of transitions (simplifying the PLL filter circuits) and with an equal number of ones and zeros (making possible some neat tricks for DC-level restoration and duty-cycle compensation).
If you work for a semiconductor company, I hope you'll take note of this concept. Scrambled clocks significantly improve radiated emissions without adding jitter.
POINT TO REMEMBER
Transmission Line Parameters
Pcb (printed-circuit board) Traces
Generic Building-Cabling Standards
100-Ohm Balanced Twisted-Pair Cabling
150-Ohm STP-A Cabling
Time-Domain Simulation Tools and Methods
Points to Remember
Appendix A. Building a Signal Integrity Department
Appendix B. Calculation of Loss Slope
Appendix C. Two-Port Analysis
Appendix D. Accuracy of Pi Model
Appendix E. erf( )