Power and Ground Resonance

Article first published in EDN Magazine , September 1, 1998

Many engineers believe that solid power and ground planes in a digital pcb should act as a large, perfect, lumped-element capacitor. Ideally, a perfect lumped-element capacitor of this size should provide a very low impedance between V CC and ground at very high frequencies (several hundred MHz and higher). When a gate demands current from the power system, such a capacitor should supply that current with very little short- term voltage sag, or droop, according to the rule i = C dv/dt .

I wish the world were that simple. The problem is, the planes do not form a perfect lumped-element capacitor. Instead, they comprise a distributed system of surprising complexity.

The distinction between a distributed system and a nondistributed (or lumped-element) system involves the relationship between the time delay of the system and the risetime of your signals. As long as the time delay is sufficiently short, you might reason that it hardly affects the results and may be safely ignored. For example, if your pcb dimensions are 6 in. by 6 in., the time delay for signals trapped between the V CC and ground planes as they travel from one side of the board to the other is approximately 1 nsec (for an FR-4 substrate). If you are using logic with a rise/fall time in the vicinity of 5 nsec, the lumped-element condition is mostly satisfied, and the planes will act to your benefit as one, large, parallel-plate capacitor.

Fast drivers perceive the power-and-ground structure as a distributed object with a significant delay.

 

What happens with much faster logic? With 200 psec rise/fall times, the drivers perceive the power-and-ground structure as a distributed object with a significant delay. This delay causes a number of artifacts. First, during an individual rising or falling edge, only the portion of the planes located within a small radius of the driver can react before the rising (or falling) edge is over and done. As a result, the initial noise spike may be much larger than you had anticipated. Next , the residual power-system noise signals from that first event travel across the board, bump into the edges of the board, reflect, and then finally return, a couple of nanoseconds later, to the driver location. If at that precise moment, the driver switches a second time, you will see both the old reflected response from the first signal and a response to the second signal superimposed together. If the phases add, you get more noise at the second edge than at the first. If the driver continues to act in a repetitive manner (like a clock), the reflected noise will build to a significant degree. This behavior exemplifies a resonant mode in the power system. In severe cases, resonance in the power system can cause your product to fail to function.

If your next system design depends on the natural power-plane capacitance to limit power supply noise, check to see how the round-trip delay across your board compares to your clock period. If it's close, consider building a test board mock-up (just use a plain, double-sided FR-4 core ). With this setup, you can directly measure the impedance between the planes using a network analyzer to check for resonance. Another possibility is to take advantage of the latest power-system simulation tools. Several CAD vendors have developed packages that can simulate the distributed nature of a power-plane pair. These packages can help you evaluate the effectiveness of bypass capacitor placement, and also detect any resonance due to the shape and configuration of the planes.

Figure 13.9 illustrates the output from one such package. The structure it depicts contains 6 metal layers , (Signal, Power, Signal, Signal, Ground, Signal) as shown in the bottom part of the figure. The graph above shows the spatial distribution of voltage between the power and ground planes during transient simulation. The ripples near the center of the board emanate from an active driver. The de-coupling capacitors mounted on the board are placed to minimize the fluctuations. You can identify the locations of the decoupling capacitors from the dents in the graph.

Figure 13.9. The magnitude of noise varies in a complicated way across the surface of a power plane. (Picture courtesy of Sigrity, provider of software tools for the detailed analysis and design of signal and power delivery systems in high-speed digital products.)

If you haven't seen this category of tools, ask your CAD vendor for a demo. It's time well spent (and the 3-D graphics look really cool).

POINT TO REMEMBER

• If your system design depends on the natural power-plane capacitance, compare the roundtrip delay across your board to your clock period ”you could be headed for resonance problems.

For further study see: www.sigcon.com