The spread between V IL and V IH creates an uncertainty in the exact moment at which a clock receiver will switch. This uncertainty is a normal part of any skew budget, although it may be accounted for in many different ways. For example, input setup times might be referenced to the instant the clock satisfies V IL , while input hold requirements are referenced to the instant the clock satisfies V IH .
Figure 12.20 illustrates the relationship between the signal risetime, signal amplitude, and the uncertainty (or skew) contributed by the effect of uncertain thresholds. Differential receiver families with tight control over V IL and V IH contribute very little skew due to threshold uncertainty.
Figure 12.20. Always incorporate the clock receiver switching uncertainty in your skew budget.
While you cannot much improve the basic uncertainty of a logic family by using an exceptionally fast clock input (because the clock receiver won't respond any faster than normal anyway), you can disadvantage your system by using an overly slow clock waveform, exacerbating the effect of uncertain thresholds.
POINT TO REMEMBER
Transmission Line Parameters
Pcb (printed-circuit board) Traces
Generic Building-Cabling Standards
100-Ohm Balanced Twisted-Pair Cabling
150-Ohm STP-A Cabling
Time-Domain Simulation Tools and Methods
Points to Remember
Appendix A. Building a Signal Integrity Department
Appendix B. Calculation of Loss Slope
Appendix C. Two-Port Analysis
Appendix D. Accuracy of Pi Model
Appendix E. erf( )