The following sections describe the main applications for differential signaling on pcbs.
6.11.1 Matching to an External, Balanced Differential Transmission Medium
Differential traces are often used to connect to balanced cabling. For this purpose, the tightness of coupling between the two traces making up the differential pair is irrelevant. What matters is that the differential characteristic impedance of trace configuration matches the differential characteristic impedance of the balanced cabling.
The most popular types of balanced cabling are 100- W twisted-pair cabling (ISO 11801 categories 3, 5, 5e, 6, and 7), and the old 150- W shielded twisted-pair cabling (IBM Type I). When connecting directly to these cabling types, one normally uses two 50-ohm traces (or two 75-ohm traces for 150- W cabling) to couple into the cable.
Figure 6.21 depicts a typical LAN coupling situation. The target cable is a 100- W unshielded twisted-pair cable. Your objective in this application is to generate a purely differential transmitted signal of standard size with as little high-frequency power and as low a common-mode content as practicable.
Figure 6.21. Ethernet 10/100BASE-T interface, showing use of 50- W transmission lines to match 100- W balanced load.
The low-pass filter formed by L1-C1 (and L2-C2) truncates any unnecessary power in the frequency range above the bandwidth of the digital signal. The natural balance of the transformer combined with the additional balancing properties of the common-mode choke together serve to limit the common-mode content of the transmitted waveform. The reason common-mode balance is so important is that common-mode radiation from an unshielded twisted-pair cable is many orders of magnitude more efficient than differential-mode radiation. Minimizing the common-mode current minimizes the cable emissions.
After passing through the common-mode choke you should make the two pcb traces as symmetrical as possible, with equal impedances to ground. The traces must be symmetrically positioned with respect to all nearby grounded objects, but they do not necessarily need to be tightly coupled to each other.
POINTS TO REMEMBER
6.11.2 Defeating Ground Bounce
Differential signals arrive naturally at a receiver with a built-in reference voltage. The receiver of a differential signal need not rely on its own internal reference, which could be corrupted by ground bounce or other disturbances in the reference supply. Differential signaling defeats ground bounce.
For ground-bounce cancellation to work, the receiver must see two complementary signals with equal delays from the driver. Any ground shifts or disturbances along the way that affect both wires equally will be cancelled at the receiver.
Note that the two halves of a differential signal must arrive synchronously so that they will be equally influenced by noise, but they do not necessarily need to be tightly coupled to each other.
POINT TO REMEMBER
6.11.3 Reducing EMI with Differential Signaling
Differential signals radiate less than single-ended signals. That's one of the benefits of differential logic. If the two complementary signals of a differential pair are perfectly balanced, the degree of field cancellation is determined entirely by the separation between traces.
If, however, the two complementary signals are not perfectly balanced, then the degree of attainable field cancellation will be limited to a minimum value determined not by the trace spacing, but by the common-mode balance of the differential pair. Because the common-mode balance of most digital drivers is not particularly good, it often happens that differential pairs radiate far more power in the common-mode than in the differential mode. In such a situation no radiation benefit remains to be gained from squeezing the differential traces more closely together.
Figure 6.22 plots the theoretical radiation gain attained by a differential microstrip pair as a function of trace separation. The figure assumes the measurement antenna is located in the plane of the board, removed in a broadside direction a distance r = 10 m away from the traces (worst case). The radiation from one trace of the differential pair is supposed to be cancelled by the equal and opposite radiation from the adjacent trace, resulting in a marked reduction in emissions. The depth of cancellation is related to the ratio 2 p s / l , where l is the free-space wavelength of the highest frequency of interest and s is the separation between traces. This ratio controls the relative phase relationship of the two near-complementary waves as they leave your board. The cancellation is also related to the ratio r /( r + s ), which speaks to the relative intensities of the two near-complementary waves as they reach the antenna. The formula in Figure 6.22 shows that differential cancellation improves as you reduce s .
Figure 6.22. Theoretical radiation improvement a for the differential portion of the far-field radiation from a microstrip, as a function of trace separation s .
The common-mode radiation from the two traces of a differential microstrip reinforces rather than cancels, so that common-mode radiation does not vary strongly with trace separation. You can adjust the differential-mode radiation by adjusting the trace spacing, but you can't do much about the common-mode radiation (except to install a driver with better common-mode balance).
Under FCC class B measurement conditions, the differential-mode radiation from a differential microstrip pair with 0.5-mm (0.020-in.) separation should theoretically yield a 40-dB radiation improvement at 1 GHz, compared to the radiation measured if the same signal were implemented as a single ended layout. Smaller separations should yield even more improvement. While that theory sounds appealing, in practice you will rarely if ever achieve as much as a 40-dB improvement in overall radiation because your gains will be limited by the degree of balance available on the two outputs of your differential transmitter. Unless the outputs are balanced to better than 1 part in 100, a common-mode radiation component of at least 1% of the differential amplitude will emanate from your differential pair anyway. Given a 1% common-mode imbalance, even a differential spacing of zero would not improve the total radiation by more than 40 dB.
Taking an example from the LVDS differential driver family, which prescribes a differential balance no better than 1 part in 16, even the most Herculean efforts at trace balancing will never improve the overall radiation for that logic family by more than a factor of 16 (24 dB).
In plain terms, a differential trace spacing of 0.5 mm is close enough to deliver all the EMI benefit you are likely to ever achieve. Because radiation problems on digital pcbs are usually dominated by the common-mode radiation, you need not struggle to place ordinary differential digital traces any closer than 0.5 mm for any EMI purpose.
POINT TO REMEMBER
6.11.4 Punching Through a Noisy Connector
When two systems are mated by a connector, the net flow of signal current between the systems returns to its source through the ground (or power) pins of the connector. As it does so, tiny voltages are induced across the inductance of the connector's ground (or power) pins. These tiny voltages appear as a difference between the ground (or power) voltage on one side of the connector and the ground (or power) voltage on the other side. This problem is called a ground shift , and it is yet another form of common impedance coupling. In a single-ended communications system the ground shift voltages detract directly from the available noise margin for your logic family. In a differential signaling system, the ground-shift voltages don't matter, because they affect both wires of the differential pair equally. Subject to the limits of common-mode rejection , ground shifts generated within a connector are totally cancelled within the receiver.
Differential signaling usually reduces crosstalk generated by either mutual inductance or mutual capacitance within the connector itself. The exact gains available depend on the relative spacing of the differential signals as they pass through the connector and the distance to the nearest aggressive source. If the aggressive source is closer to one element of the pair, the crosstalk will not affect both pairs equally, and it will therefore not be cancelled in the receiver.
The cancellation of ground shifts generated by a connector and the cancellation of nearby aggressors within a connector both have a lot to do with the position of the signal pins within the connector, but very little to do with the pcb trace layout, or intertrace coupling.
POINT TO REMEMBER
188.8.131.52 Differential Signaling (Through Connectors)
High Speed Digital Design Online Newsletter , Vol 3, Issue 12 Sal Aguinaga writes
I have 16 differential pairs that go through a connector and terminate on a daughter card. What is the best signal-to-ground ratio and pattern I should consider?
In this case the connector is a high-density pin connector. If the differential impedance is 100 W , do I need a special ground pattern as the signals go through the connector to maintain the differential impedance close to 100 W ?
Thanks for your interest in High-Speed Digital Design .
Regarding your correspondence, there is no general formula for the number of grounds required, as it depends on the spacing and sizes of the connector pins, and how they are bent.
Here are a few thoughts for you to consider.
The differential impedance of most open-pin-field connectors is probably going to be a little higher than you want. You can measure this. You will need a pair of test boards on which you can mate the connector halves. The boards don't use any traces. They can be solid copper with holes drilled for the connector pins. Ground all the pins that will be grounded (or tied to a power plane) in your application. Use two RG-174 50- W coaxial cables to route a differential, 100- W signal into the designated signal pin pair. Let this signal go through the connector to the far side. On the far side of the connector, terminate the signal differentially with 100 W .
For any signal speed that will work with an open-pin-field connector, you will find that a 1/8-watt axial , 100- W resistor works fine as a terminator.
Blast in a differential signal from your 100- W source. Make a record of the resulting waveform as measured at the source. This should show the source waveform going out and a first reflection coming back (you've made a crude TDR instrument). Use a step risetime commensurate with what you are going to be using in the real system.
Don't mess around with fancy 35-ps step edges on this type of connector. They will just show you a bunch of fine-structure detail that isn't going to matter in the real system.
Now disconnect the coaxial cables from the connector. Place the 100- W termination directly across the coaxial cable outputs, with the coaxial grounds tied together. Repeat the measurement. You should ( ideally ) see no reflection.
Looking at the difference between the first measurement and the second, if the reflected waveform bumps up in the positive direction (same polarity as the step input), the connector impedance is a little too high. If it bumps negative, the connector impedance is too low. If you don't see a bump then the impedance is just right.
Adding more ground pins around the signal pair lowers the impedance.
Spacing the signal pins further away from ground raises the impedance.
Bonus idea: Adding a little lumped-element capacitance from signal to ground on each side will lower the effective impedance. This may be implemented in the pcb layout by just using larger-than-normal via pads. Experimentation and remeasurement is required to get this idea to work. The "big-pad" concept works when the connector through-delay is less than 1/6 of the signal risetime and the connector is acting like a lumped-element inductor (too high an impedance).
 Connectors with solid ground shields between columns of pins are usually designed to accommodate differential pairs collocated within each shielded cavity . This implies that the pin lengths may differ for the two elements of each pair. A perfect differential shielded connector would be designed to match the skew on each element of a differential pair as it traverses the connector, even if the elements were located on different rows. If your connector produces a known skew, it's up to you to cancel it somewhere else in the layout.
6.11.5 Reducing Clock Skew
When a digital component receives a clock, the precise moment at which the clock is recognized depends upon the switching threshold for that component. For 5-V TTL logic, the switching threshold is defined to be somewhere between 0.8V ( V IL ) and 2.4V ( V IH ). The spread between V IL and V IH defines a window shown in Figure 6.23 within which the actual clock transition takes place:
t UNCERTAINTY is the uncertainty (skew) in the clock switching moment,
V IH and V IL are the worst-case guaranteed high and low logic thresholds respectively, and
dv / dt is the rate of change of voltage on the clock input ( roughly equal to the logic swing D V divided by the 10% to 90% risetime of the driver). 
 The risetime emanating from an unreasonably fast driver will be modified by the package parasitics of the receiver. The risetime of the signal measured at the input pads of the receiver die is therefore generally not quite as fast as the risetime measured external to the package. It is the risetime of the internal signal combined with the receiver switching thresholds that determines the actual amount of switching uncertainty. If the driver and receiver are implemented in similar technology, and the package is not deemed a significant impediment to reception , you may simply use the driver risetime for the calculation of dv/dt in equation [6.25].
Figure 6.23. The input thresholds and the risetime of the input signal combine to create an uncertainty in the precise switching time for a clock.
The smaller you can make this uncertainty, the less clock skew you will have to recognize in your timing budget. In the differential world a similar effect takes place, but the specifications for V IH and V OL are replaced by a specification for the offset voltage of the receiver. The input offset voltage is the differential input voltage at which a particular receiver actually switches. An ideal receiver would switch precisely at zero (when the inputs are equal), regardless of common-mode voltage, temperature, power supply quality, age, and so on. Such a part would have an input offset voltage of zero. Practical receivers always switch at some finite, hopefully small, value. There is no way to predict the polarity of the offset.  The spec sheet for a differential receiver usually provides a worst-case upper bound for the magnitude of the offset. The effective spread between V IH and V IL for a differential receiver is twice the maximum offset magnitude.
 Unless the device is manufactured with a purposeful offset in one direction or another.
A relevant figure of merit for comparing differential logic families in this regard is the ratio of the spread in differential input offset voltage to the peak-to-peak differential output voltage swing.  For single-ended logic the corresponding figure of merit is the spread between V IH and V IL divided by the peak-to-peak output voltage swing. Differential logic usually fares better on this measure of performance.
 In a differential signaling architecture, the peak-to-peak differential output voltage swing is twice as large as the peak-to-peak voltage swing on either of the two inputs.
In a differential clock distribution system one usually attempts to match the delays of the two complementary signal traces as they traverse a pcb. The two traces need not follow the same path ; they just need to have the same delay. If the delays of the two traces are unequal , if affects the switching time. For example, suppose the two complementary halves of a differential signal arrive at successive times t 1 and t 2 . Let the separation between t 1 and t 2 be a small fraction (perhaps 1/10) of a rising edge. Under these conditions the receiver will switch very nearly at the average arrival time ( t 1 + t 2 )/2. In the worst case, if the separation is as great as a risetime, the receiver will switch no earlier than t 1 and no later than t 2 . I normally match the delay of the two traces in a differential signal to within 1/20 of the signal risetime.
The clock skew contributed by a clock receiver is a function of the input risetime, the switching thresholds, and, for differential signaling, the degree of similarity in the times of arrival of the two complementary signals. Clock skew has little or nothing to do with trace spacing or geometry (other than delay).
POINTS TO REMEMBER
6.11.6 Reducing Local Crosstalk
Differential traces on a pcb do a relatively poor job of reducing local crosstalk. As illustrated in Figure 6.24, when some local aggressive trace approaches a differential pair, the interference is not balanced. Interference couples much more strongly to the near side of a differential pair than to the far side.
Figure 6.24. Differential signaling does not offer much help with nearby crosstalk.
In the figure, clock+ is twice as close to the aggressor as clock “, so you get a 4:1 difference in the crosstalk coupled into the two sides. Imbalanced crosstalk of this sort cannot be cancelled by a differential receiver. The receiver sees almost the full value of crosstalk from the aggressive trace to the clock+, with little or no cancellation from clock “.
The best way to prevent crosstalk onto a differential pair is to design a keep-out zone around the sensitive traces, forcing other traces to stay at a respectable distance. All modern layout systems support separation rules by net class that will allow you to keep big, dirty signal traces away from delicate, sensitive ones.
Cramming the traces of a differential pair closer together does yield marginal improvements in crosstalk reduction, but you don't get the big benefit you get from simply moving the whole pair further away from the problem. Figure 6.25 provides data to support this assertion. The data for this plot were generated using a sheet- conductance measurement method  .
Figure 6.25. The crosstalk immunity of differential pairs is not much improved by tight coupling; mostly what matters is the interpair spacing.
The figure plots crosstalk for three trace configurations. Each plot shows the measured near-end crosstalk coefficient in dB versus the separation x between traces. 
 Measurements performed using salt-water tank per Howard Johnson, "Rainy-Day Fun," EDN Magazine , March 4, 1999. This data has been corroborated against a commercial 2-D field solver.
The first scenario shows how a single-ended aggressor affects a differential pair. The next two scenarios show how two differential pairs affect each other. The difference between scenarios II and III is that the intrapair separation changes from 8 to 4 mils. In all cases the separation between planes is 24 mil, and the height of all traces above the nearest plane is 6 mil. The widths of all traces have been adjusted to give a characteristic impedance of 100 ohms for all differential transmission-line pairs and 50 ohms for the single-ended aggressor.
In all cases the crosstalk falls off steeply as you increase the separation x between the aggressor and victim. Looking at the difference between scenarios I and II, the addition of a complementary signal to the aggressor (changing it into a differential pair) tends to cancel a little bit of the interference, but the complementary signal is too far away to have much of an effect. The net reduction in interference is less than 2 dB. When you go from scenario II to III, reducing the intrapair separation, the complementary signals is brought into play. This reduces crosstalk by an additional 4 dB, which is useful, but still nowhere near as significant as simply moving the aggressor further away.
Tightly coupling a differential pair delivers only a modest improvement in crosstalk, and therefore only a modest improvement in the achievable pair pitch (see also Section 6.10.2, "Edge-Coupled Stripline ").
POINT TO REMEMBER
6.11.7 A Good Reference about Transmission Lines
The Transmission Line Design Handbook by Brian C. Wadell  compiles handy approximations for transmission-line impedance, delay, skin effect loss, dielectric losses, and radiation losses. It is very comprehensive. The book addresses most of the popular transmission-line formats in use today, including microstrip, buried microstrip, offset stripline, and edge- or broadside-coupled differential striplines.
Wadell heavily references the original research articles and measurements. He doesn't pull any punches when the research is fuzzy or contradictory. He shows you just what is known and indicates what is not known. If you're looking for closed-form approximations, this is the best source.
P.S.: If you have an old copy of Wadell's text, check out his errata list on the Web.
6.11.8 Differential Clocks
High Speed Digital Design Online Newsletter , Vol 1, Issue 10 Fabrizio Zanella writes to the SI List
I understand the benefits of using differential pairs for signals running at 100MHz and above. Can you speak about the impact of using differential clocks in a parallel bus? Do the differential clocks maintain the noise suppression characteristics when daisy-chained in a multidrop environment? Has anyone tried this and had positive experiences versus single-ended multidrop clocks?
Thanks for your interest in High-Speed Digital Design .
In general, I have found differential distribution to be a very effective means of combating ground bounce in the transmitting package, ground bounce in the receiving package, as well as the ground shifts that occur on either side of the connectors in high-speed systems. These benefits accrue in multidrop configurations as well as point-to-point configurations.
I have found differential distribution to be of little value in reducing the impact of crosstalk generated locally by other traces on the same pcb. This is because the crosstalk function from nearby traces falls off very steeply with distance. The impact of this is that differential pairs cannot be placed particularly close to any aggressive signal. For example, imagine a system that has one aggressive trace and a nearby victim trace that is receiving unacceptable amounts of crosstalk. Now I propose to protect the victim trace by splitting it into a differential pair and using a true differential receiver. Assuming that I don't want to affect the layout density, I plan to implement the centerline of the new pair right on top of the original victim trace. In other words, when we split the victim, one member of the pair will have to move closer to the offending source, while the other moves away. Unless the two traces of the pair are extremely close together (less than a third of the original separation between centerlines), the extra crosstalk we pick up from the nearby side of the differential pair overwhelms any "balancing" effect we might have hoped to gain from the far side of the differential system. To mitigate this effect, you have to separate the victim pair from the aggressive signal. In the final analysis, it's usually the extra separation that is providing most of the crosstalk benefit, not the fact of balanced signal distribution. When you want to battle crosstalk picked up on a pcb (over a solid ground plane), increasing the trace separation will probably result in a more dense design than using differential distribution.
For clocks, I see differential signaling used a lot, both in point-to-point distribution and in multidrop distribution. The multidrop aspect does not diminish the ground-bounce-canceling properties of differential signaling. There are only a few clock nets in a system (compared to the number of data nets ) and it isn't that difficult to provide this extra measure of protection.
For parallel bus signals, I rarely see differential distribution used because it doubles the number of wires required. That will cause the phenomenon known as "routing headaches " among your pcb layout staff.
POINT TO REMEMBER
6.11.9 Differential Termination
Article first published in EDN Magazine , June 8, 2000
I am designing a piece of equipment to interface to a digital tape recorder designed by another company. This recorder uses a differential ECL interface, and the user 's manual recommends terminating the clock lines slightly differently from the data lines. Each clock line employs a split terminator (160- W to “5.2V and 100- W to ground), but the data signals simply use a single 120- W resistor between the wires of each pair. Because these two methods are Thevenin equivalents, why does the user's manual recommend different termination schemes? As far as I can tell, the transmitters and receivers for the clock and data lines are electrically equivalent, and all signals have 390- W pull-down resistors to “5.2V at the transmitter to properly bias their emitter-follower outputs. I have contacted the company that designed the circuit, but the original designers are unavailable. Does one termination scheme have any advantage over the other?
Engineers often have a difficult time figuring out why something was done. Sometimes there is no reason, sometimes there is a multitude of good reasons, and sometimes (as is common in the standards world) everyone wants it done the same way but all for conflicting and different reasons.
Anyway, differences do exist between the termination schemes you described. The single-resistor scheme (120 W across the two lines) terminates all differential-mode signals into 120 W but provides no termination for common-mode signals.
Your four-resistor scheme (independent terminations for each line) terminates all differential signals and all common-mode signals. The difference between these two styles matters only if a common-mode signal is present. And where might a common-mode signal come from? It can come from any skew naturally present in the clock driver output plus any imbalances in the circuit that convert part of the output from the differential mode to the common mode.
Every long, differential link needs a differential termination for signal quality and also a common-mode termination to prevent common-mode resonance .
Consider the single-resistor termination shown in Figure 6.26. Say that a positive-going edge x ( t ) arrives first on trace A, and then, after a tiny skew interval D t , the opposite signal “ x ( t “ D t ) arrives on trace B. During the tiny skew interval D t , the single 120- W resistor R1 creates two tiny artifacts. First, the initial rising edge on line A shoots right through the resistor onto trace B, creating a little blob of crosstalk. The amplitude of the crosstalk compared to the amplitude of the incoming signal is 1/2. Second, coincident with the crosstalk, you get a small signal reflected back onto line A. The amplitude of the reflected signal compared to the amplitude of the incoming signal is also 1/2. Both artifacts have positive polarity, creating what amounts to a common-mode reflection.
Figure 6.26. A network of two resistors terminates each half of the differential pair independently.
After time D t , the opposite signal “ x ( t “ D t ) arrives on line B. At this time you get a second set of crosstalk and reflection artifacts, but with negative polarities this time (because they originated on the negative half of the differential pair). The second set of artifacts partially cancels the first, with the degree of cancellation depending on the exact temporal alignment of the two signals. The two sets of artifacts perfectly cancel only when the signals on A and B arrive in perfect synchronism.
In this example, both the crosstalk and reflection amplitude coefficients equal 1/2. You may express the residual common-mode signal g ( t ), induced on either trace by the single-resistor end-terminator, as g ( t ) = (1/2)( x ( t ) “ x ( t “ D t )). If the skew is less than the signal rise or fall time t 10 “90 , and you define the signal step height as D V , the peak amplitude of the reflected common-mode noise roughly equals (1/2) D V ( D t / t 10 “90 ).
Once created, the common-mode noise returns to the driver. In your case, the ECL driver presents a very low output impedance to the line, generating a big reflection. The reflected noise then proceeds to the receiver, where it once again encounters the single-resistor termination, but this time as a purely common-mode signal. Because a common-mode signal presents the same voltage on both traces, the single-resistor terminator draws zero current and acts as an open circuit. The open circuit generates another big reflection. After that point, the common-mode noise trapped on the line happily bounces back and forth between the driver (low impedance) and the receiver (open circuit) for a long time.
Terrible things happen to the common-mode noise if your trace delay equals one-quarter of the clock period. In that case, the little common-mode artifacts from each edge build and superimpose, cycle after cycle, magnifying the common-mode noise at the receiver and also magnifying the common-mode radiated emissions. This problem is called a common-mode resonance .
To avoid common-mode resonance, every long, differential link needs two terminations: first, a good differential termination at one end or the other to provide good differential signal quality, and second, a reasonable common-mode termination at one end or the other to prevent severe common-mode resonance. An ECL driver does not provide a good common-mode termination at the source; therefore, one is required at the load.
The four-resistor termination that was recommended to you for the end of the clock net independently terminates both lines, damping both differential and common-mode signals at that point.
An even better termination circuit appears in Figure 6.26. This circuit terminates both differential and common-mode signals but requires only two resistors (R2 and R3 are each set to half the differential-line impedance). The capacitor need be only large enough to hold its charge steady during the brief interval of skew D t . In your case the ECL sources incorporate pull-down resistors, so you don't need to supply a special terminating voltage ( V T ) to the capacitor.
Any driver that provides a reasonable common-mode termination at the source relieves you of the responsibility of providing one at the destination. For example, a source- terminated driver works fine with the single-resistor termination.
POINT TO REMEMBER
6.11.10 Differential U- Turn
Article first published in EDN Magazine , September 1, 2000
What is the effect of a split in a solid plane on the impedance of a coplanar differential pair? The differential pair passes over a solid plane (logic return) and then crosses a 50-mil void into an I/O area that has a solid plane of its own that is tied to the chassis .
Significant currents flow on the solid reference plane beneath your differential traces. Cutting the plane interrupts these currents.
Consider first a single-ended pcb trace. When a changing voltage propagates down a single-ended transmission structure, currents flow through the distributed capacitance of the trace to all nearby objects, especially the big, solid plane underneath the trace. This capacitive effect generates a returning (reverse) flow of current on the solid reference plane. The return current flows all the way back to the source along the reference plane, staying underneath the signal trace the whole way, making a complete circuit. (Current always makes a loop.)
Counteract the U-turn by shrinking both the reference-plane gap and the spacing between traces .
Now, consider a differential-pcb-trace pair. Differential structures have capacitance from each trace individually to the reference plane and also between the traces. The between-trace, or mutual, capacitance of the differential pair induces returning current on the other trace as well as on the solid reference plane. In a differential-pcb pair, most of the returning current from each trace still flows on the solid plane, not the other trace, because each differential trace couples much more strongly to the big, solid nearby plane than it does to its little, skinny differential buddy.
Try to visualize the propagation of a differential signal as a quad of four currents: two currents, i+ and i “, on the two signal traces, and the returning currents, r+ and r “, on the reference plane underneath the traces (Figure 6.27). In most cases the currents are almost as big as i+ and i “.
Figure 6.27. The U-turn zone at a reference-plane gap separates the return currents from the primary signal currents on traces A and B.
When a differential signal encounters the gap between reference planes, the two signal currents continue across the gap on the signal wires, but the gap blocks the two return currents r+ and r “. This situation forces the return currents to execute a U-turn maneuver, whereby each return current U-turns into the other position. On the new reference plane, a similar effect takes place with a second U-turn formation creating a pair of currents r'+ and r' “ to complete the quad current formation.
In the space between the reference planes, current circulates clockwise on all sides of the U-turn zone. This current behaves like a small current-loop antenna, generating a substantial, fast-changing magnetic field within the U-turn zone.
The magnetic field makes the circuit behave as if an inductor were in series with the signal path. The length and width of the U-turn zone determine the inductance. For example, a trace-to-trace separation of 0.100 in. and a plane-to-plane separation of 0.100 in. would generate an inductance on the order of 10 nH, which in a 100- W differential system would introduce a low-pass filter response with a time constant of 100 psec. If risetime exceeds 1 nsec, you probably won't even notice the effect. On the other hand, at very high speeds, a 100-psec risetime could mess up your signals.
The U-turn zone is more than merely a region of increased impedance due to the absence of the reference planes. It is an effect whose physical dimensions span both the gap between planes and the spacing between traces. You counteract the U-turn by shrinking both the reference-plane gap and also the spacing between traces. You can also practically eliminate it by providing continuous pathways adjacent to each signal trace for the conveyance of return currents from plane to plane, eliminating the need for a U-turn zone. If the planes carry different DC voltages, a bypass capacitor next to each trace isn't perfect, but it helps.
The magnetic fields within the U-turn zone induce crosstalk and EMI. The crosstalk couples to all the differential pairs that pass over the same gap. Both EMI and crosstalk vary in proportion to the size of the U-turn zone.
POINT TO REMEMBER
6.11.11 Your Layout Is Skewed
Article first published in EDN Magazine , April 18, 2002
Passing through a sharp turn with an edge-coupled differential pair, the outside trace travels further than the inside trace. The difference in distance traveled contributes a small amount of skew to your differential signals. The skew acts as a mode converter, changing part of your differential signal power into common-mode power.
The pair-turning skew becomes noticeable only when the skew contributed by the turn rises to a level comparable with the natural skew already coming out of your driver. Therefore, before worrying about turns, first determine the skew of your driver. In many cases the driver skew is not specified, in which case you can assume the skew will be at least 10% of the signal risetime. Digital differential drivers just aren't balanced very well. Analog transceivers often are, which accounts for the importance of meticulous skew-matching in some analog applications.
Chamfering or rounding of differential corners does not eliminate skew .
For example, let's say an Ethernet 100BASE-TX LAN transceiver with a well-balanced output transformer and common-mode choke puts out differential signals balanced to 1 part in 1000 ”meaning that the common-mode output is 1000 times smaller than the differential signal. To avoid amplifying the common-mode signal on the wires (and thereby the radiation), the aggregate skew contributed by all components used with this transceiver must remain less than 1/1000 of 1 risetime. The risetime of a 100BASE-TX signal is approximately 8 nS, corresponding to roughly 94 inches of propagation in air, 1/1000 of which works out to 0.094 in., so the skew budget within cable connectors and board layout should be set somewhere around 0.1 inch. Worrying about little bitty skew effects much smaller than 0.1 inch doesn't buy you anything.
To take a faster example, a 2.5 Gb/s serial link driver with a risetime of 200 ps has an output skew of probably no better than 20 ps (maybe a lot worse ). In this case a skew budget of perhaps 20 ps seems reasonable.
Figure 6.28 illustrates the skew calculations for three alternative corner treatments , each with a trace pitch (centerline to centerline) of p . In each case, the two traces within the pair share the same number and type of sharp corners (diagonal-striped regions ). The differences between the inside and outside traces are shaded dark with white lettering. The lengths added to the outside trace are 2 p , 1.65 p , and 1.57 p respectively for the three corner styles. Apparently, chamfering or rounding of differential corners does not eliminate skew; it only makes at best a modest improvement.
Figure 6.28. These three corner treatments all generate similar amounts of skew.
If your trace separation p equals 20 mils, and the propagation delay of your media is 160 ps/in., the skew associated with a distance of p is (0.020 in. x 160 ps/in.) = 3.2 ps. According to Figure 6.28, the skew accumulated when rounding a corner of any of the three types shown ranges in that case from a high of 2 p 6.4 ps to a low of 1.57 p 5.0 ps. If this amount of skew is superceded by the skew from your driver, then don't worry about the turns.
When skew becomes a problem, you can mitigate its impact in two ways. First, use a smaller spacing. The smaller you make p , the less skew you will get. This is one of the few benefits of tightly coupled pairs. Second, position your ICs so the traces leave the driver headed in the same direction that they enter the receiver. For example, a differential pair that starts out headed north and ends up headed north has by definition equal numbers of right- and left-hand turns no matter what happens in the middle (unless it makes a spiral), so the net skew accumulated is zero.
POINT TO REMEMBER
6.11.12 Buying Time
Article first published in EDN Magazine , May 2, 2002
The previous article "Your Layout Is Skewed" concerned various styles of corners and bends normally used on differential edge-coupled pairs. It pointed out that all corners, whether chamfered or not, add extra length to the outside trace as it rounds the bend. The equivalent trace length added by 90 worth of bending ranges from one and one half to two times the intrapair trace pitch depending on how the corner is chamfered. The extra time added to the outside trace is a form of intrapair skew.
This article considers two strategies for minimizing the intrapair skew accumulated by a differential net. The six BGA chips within the dotted -line region in Figure 6.29 illustrate the first strategy.
Figure 6.29. The positioning of entrances and exits affects the intra-pair skew.
Pair A exits the bottom chip heading north. It enters the receiver (top chip) also heading north. Along the way, this pair takes one right turn and one left turn. The skew accumulated in the two successive turns cancels to zero .
In a general routing problem, the number and types of turns required depends on the relative orientations of the driver and receiver. Because pair A starts and ends going in the same direction, this pair will always make equal numbers of right-hand and left-hand turns no matter what happens in the middle (unless it makes a spiral). The net skew accumulated on any pair with a chip floor plan like A is zero.
Pair B doesn't fare as well. It exits the bottom chip headed east. It takes one left turn to get going north (the orientation of the receiver), after which the number of left and right turns remain balanced. The total skew accumulated by pair B equals the amount generated by one left-hand turn.
Pair C is the worst of all. It exits to the east and enters to the west. It therefore requires two extra left turns to achieve the correct orientation. If you are going fast enough so that every turn worth of skew matters, you should carefully plan your chip orientations so the accumulated skew naturally balances to zero.
A pair that starts and ends going north has by definition equal numbers of right-hand and left-hand turns .
The second strategy concerns the precise manner in which your pair enters or exits a ball grid array (or any field of connector pins, package pins, or vias). This strategy works best when the ball pitch exceeds the intrapair trace pitch. It works by offsetting the centerline of the pair as it enters (or exits) the BGA, as shown in the figure at D . By offsetting the top pair down half a position, extra time delay accrues to the topmost trace. Offsetting the bottom pair up half a position adds time to the bottommost trace. This strategy "buys some time," which you can use to pay for other floor planning inadequacies. It isn't perfect, but it delivers what you need ”balanced skew.
When you have to adjust the skew, I favor doing it near either the driver or the receiver, whichever has the poorest termination. That way the skew adjustment can't possibly affect the quality of the good termination at the other end of the line. If both ends have high-quality terminations, then you place the adjustment at either end. In an imperfect world, that's as well as you can do.
To those who yearn for a perfect layout with zero bends I say, with all due credit to the Rolling Stones, "You can't always get what you waaaannnnnnnt... You can't always get what you waaaannnnnnnt... but if you buy some time, you just might find, you'll get what you need."
POINT TO REMEMBER
Transmission Line Parameters
Pcb (printed-circuit board) Traces
Generic Building-Cabling Standards
100-Ohm Balanced Twisted-Pair Cabling
150-Ohm STP-A Cabling
Time-Domain Simulation Tools and Methods
Points to Remember
Appendix A. Building a Signal Integrity Department
Appendix B. Calculation of Loss Slope
Appendix C. Two-Port Analysis
Appendix D. Accuracy of Pi Model
Appendix E. erf( )