An IBIS model specifies two IV tables for each driver, one representing the static behavior of the driver when switched to the low state and another IV curve representing the driver in the high state. In addition, the file provides other information that says how to morph from one IV table to the other (see Figure 13.5). The purpose of morphing is to produce, at each point in time, a complete IV table that a SPICElike simulation engine can use to compute circuit results.
Figure 13.5. IBIS specifies a rate at which the lowstate IV curve morphs into the highstate IV curve.
The form of the morphing information you will see inside an IBIS file depends on which version of the IBIS format you are using. The oldest (and simplest) IBIS specification included nothing more than a transition rate. The transition rate provides some gross information about how to morph from the low table to the high table, but as with any interpolation process, the exact form of interpolation used affects the accuracy of the final result. For example, software vendors that implement the transition as a strictly linear ramp create waveforms significantly different from those that use quadratic smoothing at the corners of each rising or falling edge.
More recent IBIS specifications include rising and falling waveform specifications. These specifications include samples of the (rising or falling) waveform as observed under particular measurement conditions. The measurement conditions used are called out as part of each waveform specification. There may be more than one waveform specification.
For CMOS totempole drivers, a good IBIS model provides two rising edge waveforms ”one measured with a 50 W load to ground and one measured with a 50 W load to V CC . The model also provides two falling waveforms, for a total of four combinations of behavior showing rising and falling waveforms under both load conditions.
I rate such a model as good because I believe that such measurement conditions span the range of circumstances under which critical evaluation of signal shape is most important for CMOS drivers. For emitterfollower type drivers (ECL, PECL, and some GaAs), one waveform of each type measured with a 50 W load to the appropriate termination voltage will suffice. For pulldown only drivers like RAMBUS, GTL, and BTL one waveform of each type measured with a 25 W load (or whatever is appropriate in your system) to the appropriate termination voltage will suffice.
If only one waveform of each type is to be measured for a CMOS driver it should be measured using a symmetrically split endtermination.
An IBIS simulator uses the measured waveforms to improve the accuracy of its calculations. To understand how, you need a little information about the IBIS chip model.
Your IBIS simulator assumes each chip incorporates a totempole driver, some protection diodes, and a lumpedelement capacitance representing the aggregate capacitance of the FETs and diodes (Figure 13.6). The totempole stage and the protection diodes are assumed to be memoryless, meaning that their actions can be completely described by an IV curve. The curve may vary with time, but at any instant it has a particular shape. The capacitance is assumed to be both linear and timeinvariant .
Figure 13.6. The IBIS die model includes a capacitor whose action must be deembedded from the IV table.
Your IBIS simulator is faced with the task of discovering a timevarying IV function that satisfies four constraints:
One possible way to solve this problem is to concoct a hypothetical IV function that is a linear combination of the low and high IV tables provided. [134]
[134] Not all simulator vendors use this method.
Equation 13.1
where 
i TP ( v , t ) represents the timevarying IV function associated with the totempole and diode components in Figure 13.6, 
i LOW represents the low IV table provided in the IBIS specification, 

i HIGH represents the high IV table provided in the IBIS specification, and 

a ( t ) and b ( t ) are scalar functions of time. 
The functions a ( t ) and b ( t ) are discovered by first deembedding the die capacitance from the measurements and then solving for the functions a ( t ) and b ( t ) that satisfy constraints numbered 3 and 4. The complete die model is composed of the timevarying IV relationship [13.1] placed in parallel with the shunt die capacitance. This method was described by Bernhard Unger and Manfred Maurer of Siemens AG at the February 1998 IBIS summit meeting, SIAnalysis with HSPICE based on IBIS Models (see IBIS archives at [104] ).
The deembedding of the capacitance has a direct bearing on the accuracy of the results, because the rising and falling waveforms are defined at the die, including the capacitor ( v DIE in Figure 13.6), but the IV curves you seek are defined at the output of the totempole and diode stage prior to the capacitor.
Using the rising waveform specified as part of the IBIS model, and given knowledge of the load conditions, your IBIS simulator can compute the current i DIE flowing out of the die and into the load at every point in time during one rising edge. Your simulator can also compute the current flowing through the capacitor, i CAP , assuming it knows accurately the dv / dt of the measured waveform and the value of the die capacitance. The simulator then adds i DIE and i CAP to find the current i TP coming out of the totempole stage. This calculation is called the deembedding process . After deembedding the die capacitance the simulator knows, for each point in time during the rising edge, a pair of current and voltage values ( i TP and v DIE ) which together represent one point on the IV table for the totempole stage at that particular time with that particular load.
If only one rising waveform is available the simulator uses the deembedded information to solve for a ( t ) and b ( t ) under the additional assumption that the two functions sum to unity.
If a second rising waveform is available measured under different conditions of loading, then your simulator can deduce two points on the totempole IV curve for every moment in time, which is just enough information to solve independently for the coefficients a ( t ) and b ( t ). This dualwaveform solution produces a rising edge model better suited for extrapolation to other conditions of loading.
The procedure is repeated to compute values of a ( t ) and b ( t ) for falling edges.
If the assumed die capacitance doesn't match the actual die capacitance present during laboratory measurement (or SPICE simulation), then the coefficients a ( t ) and b ( t ) will not come out quite right. The result of that inaccuracy is that waveforms predicted under conditions similar to the measurement conditions will come out just fine, but as you move away from the measurement conditions to other types of loads, the predicted waveforms become increasingly erroneous. This effect highlights a very important concept relevant to all interpolation algorithms:
Always specify circuit behavior under conditions similar to the actual conditions present in your application.
For example, highspeed drivers rarely encounter 50pF lumped capacitances in realworld applications; therefore, the old 50pF timing specification makes little or no sense. For highspeed parts , it is much better to specify the performance of your driver into a 50 W load and then extrapolate from there to determine what would happen with the occasional 50pF load.
If your waveform measurements are taken on a packaged component (at point v IO in Figure 13.7), then the entire package model must first be deembedded to determine the die waveforms. This operation is generally beyond the scope of an IBIS simulator, although it is certainly within the realm of reason that someone would take packagedchip measurements and from that attempt to intuit the die waveforms.
Figure 13.7. IBIS models a chip die and its associated package separately.
POINT TO REMEMBER
Fundamentals
Transmission Line Parameters
Performance Regions
FrequencyDomain Modeling
Pcb (printedcircuit board) Traces
Differential Signaling
Generic BuildingCabling Standards
100Ohm Balanced TwistedPair Cabling
150Ohm STPA Cabling
Coaxial Cabling
FiberOptic Cabling
Clock Distribution
TimeDomain Simulation Tools and Methods
Points to Remember
Appendix A. Building a Signal Integrity Department
Appendix B. Calculation of Loss Slope
Appendix C. TwoPort Analysis
Appendix D. Accuracy of Pi Model
Appendix E. erf( )
Notes