If we implement a linear phase FIR digital filter using the standard structure in Figure 1316(a), there's a way to reduce the number of multipliers when the filter has an odd number of taps. Let's look at the top of Figure 1316(a) where the fivetap FIR filter coefficients are h(0) through h(4) and the y(n) output is
Figure 1316. Conventional and simplified structures of an FIR filter: (a) with an odd number of taps; (b) with an even number of taps.
If the FIR filter's coefficients are symmetrical we can reduce the number of necessary multipliers. That is, if h(4) = h(0), and h(3) = h(1), we can implement Eq. (1362) by
Equation 1363
where only three multiplications are necessary as shown at the bottom of Figure 1316(a). In our fivetap filter case, we've eliminated two multipliers at the expense of implementing two additional adders. This minimummultiplier structure is called a "folded" FIR filter.
In the general case of symmetricalcoefficient FIR filters with S taps, we can trade (S–1)/2 multipliers for (S–1)/2 adders when S is an odd number. So in the case of an odd number of taps, we need only perform (S–1)/2 + 1 multiplications for each filter output sample. For an even number of symmetrical taps as shown in Figure 1316(b), the savings afforded by this technique reduces the necessary number of multiplications to S/2.
As of this writing, typical programmableDSP chips cannot take advantage of the folded FIR filter structure because it requires a single addition before each multiply and accumulate operation.
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