Article first published in EDN Magazine , March 1, 2001 by Bruce Archambeault, PhD
Many hardware-design engineers use signal-integrity-analysis software to check every trace on their boards for acceptable ringing, crosstalk, and delay. Often during this process, the termination resistors are changed to ensure that the proper voltage waveforms arrive at every receiver. Once the voltage waveforms are acceptable, the design process is complete. This process is good enough for signal integrity, but it's not good enough for EMI because most radiated-emissions problems depend more on signal currents than on signal voltages.
A range of termination resistor values often generates acceptable voltage waveforms but with vastly different currents. If you care about EMI, select the termination that generates the least current.
If you care about EMI, select the termination that generates the least current.
The relation between intentional signal current and radiated emissions works as follows : Normally, when a driver intentionally sends current down a pc trace, you expect the returning signal current to flow on the nearest reference plane, directly beneath the trace, all the way back to the source. Most of it does. EMI engineers, however, recognize that not all the return current flows directly under the signal trace. A tiny fraction of the returning signal current spreads out over the entire plane as it seeks the overall minimum inductance path back to the source. Although most of the return current remains under the trace, not all of it is there. The portion of your intentional current that spreads out and flows where you don't want it is called common-mode current. Signal integrity specialists call this stray current.
For example, suppose you route a high-speed clock trace through a via from the top layer of your board to the bottom. Along the way, you've changed the reference plane that the trace uses. When the signal current traverses the via, the returning signal current must follow along, somehow leaping from one plane to the other, possibly diverting through a decoupling capacitor along the way. Unfortunately, any layout that even temporarily diverts the signal current from its associated return path tends to greatly magnify the amplitude of stray current. If magnetic fields from the stray current couple onto nearby I/O cables or other conductors that leave your shielded enclosure, your product may not pass EMI testing.
You can reduce the level of stray currents and thus emissions in your designs by reducing the level of intentional signal current. This process is easy if your simulator shows you the current waveforms.
Figures 12.65 and 12.66 illustrate the simulated voltage and current waveforms respectively for a 30.5-cm (12-in.), 133-MHz clock net. The net is source- terminated . The voltage waveform at the receiver is shown for several source-termination-resistor values starting at 10 W . As the source-termination-resistor value increases in steps to 39 W , some pulse-amplitude risetimes lengthen, but the signal is still acceptable in all cases.
Figure 12.65. Changing the source resistance does not much affect the recevied waveform.
Figure 12.66. Changing the source resistance dramatically affects the transmitted current.
Looking at the current waveforms, you can see that the 10- W resistor allows much more current to flow than the other values allow. Further examination reveals that the 22- W and 25- W waveforms contain extra current glitches that are missing for larger resistors. At high harmonics of the clock frequency, the larger resistors reduce the current amplitude by 10 dB to 20 dB with a concomitant reduction in EMI by that same amount.
If you take the time to look at current waveforms in your simulated data, you may find similar ways to improve your emissions.
POINT TO REMEMBER
For further study see: www.sigcon.com