HyperTransportв„ў System Architecture
HyperTransportв„ў System Architecture
ISBN: 0321168453
EAN: 2147483647
EAN: 2147483647
Year: 2003
Pages: 182
Pages: 182
- Main Page
- Table of content
- Copyright
- PC System Architecture Series
- Figures
- Tables
- Acknowledgments
- About This Book
- The MindShare Architecture Series
- Cautionary Note
- Intended Audience
- Prerequisite Knowledge
- Topics and Organization
- Documentation Conventions
- Visit Our Web Site
- We Want Your Feedback
- Part One: Overview of HyperTransport
- Chapter 1. Introduction to HyperTransport
- Background: IO Subsystem Bottlenecks
- What HT Brings
- Chapter 2. HT Architectural Overview
- General
- Transfer Types Supported
- HT Signals
- Scalable Performance
- Extending the Topology
- Packetized Transfers
- HyperTransport Protocol Concepts
- Managing the Links
- Part Two: HyperTransport Core Topics
- Chapter 3. Signal Groups
- Introduction
- The Signal Groups
- The High Speed Signals (One Set In Each Direction)
- Scaling Hazards: Burden Is On The Transmitter
- The Low Speed Signals
- Where Are The Interrupt, Error, And Wait State Signals?
- No Arbitration Signals Either
- Chapter 4. Packet Protocol
- The Packet-Based Protocol
- The Two Packet Types: Control And Data
- The Need To And Data Packets
- Packet Format: Control Packets
- Chapter 5. Flow Control
- The Problem
- HyperTransport Flow Control: Overview
- Flow Control, A System View
- Flow Control Buffer Arrangement
- Example: Initialization And Use Of The Counters
- A Few Implementation Notes
- Chapter 6. IO Ordering
- The Purpose Of Ordering Rules
- Introduction: Three Types Of Traffic Flow
- The Ordering Rules
- Chapter 7. Transaction Examples
- Packets As Transaction Building Blocks
- Transaction Examples: Introduction
- Example 1: NOP Information Packet
- Generic Request And Response Packet Formats
- Example 2: Non-Posted WrSized (Dword) Transaction
- Example 3: Posted Byte Write Request
- Example 4: Dword Read Request
- Example 5: Byte Read Request
- Example 6: Flush Request
- Example 7: Fence Request
- Example 8: Atomic Read-Modify-Write
- Example 9: WrSized Request Crosses A Bridge
- Chapter 8. HT Interrupts
- Introduction
- Discovering a Device s Interrupt Requirements
- The Interrupt Message Address Range
- Interrupt Requests
- Interrupt Discovery and Configuration Capability Block
- Chapter 9. System Management
- System Management Transactions
- HT Link DisconnectReconnect Sequence
- Example SM Sequence: Link Initialization Disconnect
- Chapter 10. Error Detection And Handling
- Introduction
- The Error Types
- Error Reporting
- Chapter 11. Routing Packets
- Packet Routing: Shared Bus vs. Point-Point Topology
- Review Of Packet Types And Formats
- Directed vs. Broadcast Requests
- Accepting Packets
- Forwarding Packets
- Rejecting Packets
- Host Bridge Behavior
- HyperTransport Bridges: Additional Routing Rules
- Tunnel Fairness And Forward Progress
- Chapter 12. Reset Initialization
- General
- Cold Reset
- Link Initialization
- Warm Reset
- LDTSTOP Disconnect Sequence
- Chapter 13. Device Configuration
- HyperTransport Uses PCI Configuration
- What PCI Configuration Accomplishes
- HyperTransport System Limits
- Configuration Accesses: Reaching All Devices
- Review: How PCI Handles Configuration Accesses
- How HyperTransport Handles Configuration Accesses
- HyperTransport Configuration Space Format
- Chapter 14. Electrical
- Background and Introduction
- Power Requirements
- Differential Signaling Characteristics
- Single-Ended Signaling Characteristics
- Differential Timing Characteristics
- Testing
- Chapter 15. Clocking
- Introduction
- Clock Initialization
- Synchronous Clock Mode
- Part Three: HyperTransport Optional Topics
- Chapter 16. HyperTransport Bridges
- HyperTransport Bridges Uses PCI Configuration
- Basic Jobs Of A HyperTransport Bridge
- How Does The Bridge Manage It All?
- Chapter 17. Double-Hosted Chains
- Introduction
- Two Types Of Double-Hosted Chains
- Chapter 18. HT Power Management
- Background
- Reporting Power Management Events to the Host Bridge
- Reporting Host Power Management Events to SMC
- Reporting Power Management Events to HT Devices
- Signaling Wakeup
- X86 Power Management Support
- Chapter 19. Networking Extensions Overview
- An Important Note
- Server And Desktop Topologies Are Host-Centric
- Some Systems Are Not Host-Centric
- The Need For Networking Extensions
- Summary Of Anticipated Networking Extension Features
- Part Four: HyperTransport Legacy Support
- Chapter 20. IO Compatibility
- Introduction
- PCI Bus Issues
- PCI-X Bus Issues
- AGP Bus Issues
- ISALPC Buses
- Chapter 21. Address Remapping
- Introduction
- The Address Remapping Capability Block
- IO Address ReMapping
- DownStream HT to Expansion Bus Memory Mapping
- DMA Mapping
- Chapter 22. X86 CPU Compatibility
- Background
- X86 Interrupt Support
- The A20 Mask
- System Management Mode (SMI SMIACT)
- Numeric Error Handling (FERR and IGNNE)
- X86 Instructions and Special Cycles
- Appendix Glossary of Terms
- Index SYMBOL
- Index
- Index A
- Index B
- Index C
- Index D
- Index E
- Index F
- Index G
- Index H
- Index I
- Index L
- Index M
- Index N
- Index O
- Index P
- Index R
- Index S
- Index T
- Index U
- Index V
- Index W
HyperTransportв„ў System Architecture
ISBN: 0321168453
EAN: 2147483647
EAN: 2147483647
Year: 2003
Pages: 182
Pages: 182