Chapter 16. HyperTransport Bridges

The Previous Chapter

The previous chapter focused on the source synchronous clocking environment within HT. This involves the use of the source synchronous transmit clock to load data into a receive FIFO and the transfer of data into the receiver time domain with a receive clock that unloads data from the FIFO. Additionally, the specification defines three clocking modes that require different levels of support for passing packets between these two clock domains.

This Chapter

This chapter describes the configuration of devices which use the HyperTransport technology type 1 configuration header for bridges. Such devices include HyperTransport-to-HyperTransport bridges and bridges to other PCI compatible protocols (e.g. HyperTransport-to-PCI or PCI-X). In this chapter, the basic architecture of a HyperTransport-to-HyperTransport bridge is reviewed and the configuration header fields are described. Differences in usage of bit fields by HyperTransport bridge interfaces vs. PCI bridge interfaces are emphasized . The format of PCI compatible bridge headers is formally defined in the PCI-to-PCI Bridge Architecture Specification, Revision 1.1 .

The Next Chapter

The next chapter describes the features of the optional HyperTransport double-hosted chain topologies. Topics include the reasons behind sharing and non-sharing chains, PCI configuration space registers used to initialize the fabric for multiple hosts , and tunnel support for upstream and downstream packets moving in both directions.