X86 Instructions and Special Cycles

Another area of x86 compatibly are CPU special cycles. Most IO devices have no interest in special cycle messages. HT supports the delivery of x86 special cycles via SM broadcast messages. These messages are propagated throughout the HT topology, but are mainly of interest to chipset components , memory/cache controllers, etc. The special cycles supported by HT include:

• SHUTDOWN ” x86 processors beginning with the 80286 generate a shutdown cycle when it experiences a triple fault conditions, some models of x86 processor may also generate shutdown cycles as a result of other failures such as internal processor errors.

• HALT ” All X86 processors generate a halt special cycle when a HLT (Halt) instruction is executed.

• STOP_GRANT ” The stop grant special cycle is performed when the processor recognizes the STPCLK# (stop clock) interrupt.

• SMAF Message ” System Management Action Fields are programmed by BIOS software to define specific actions to be taken with a given message. For example, the SMAF field associated with the STPCLK message defines the power management action to be taken (e.g., a transition to an ACPI-defined power-management state).

• Voltage ID/Frequency ID Change ” Issued by the CPU if software changes settings related to Voltage (VID) or Frequency (FID)

• WBINVD ” The WBINVD (write-back and invalidate) instruction causes all modified data within the processor's internal cache memory to be written back to mail memory prior to invalidating the cache entries. As each modified line is written back, the processor invalidates that entry. Once all lines are written back and invalidated, the processor runs a WBINVD special cycle to notify external logic that all lines in the internal caches have been written back and flushed and that the external L2 cache (if present) should also perform these actions.

• INVD ” When the INVD (invalidate) instruction executes, the processor sets all cache entries to the invalid state and runs the INVD special cycle. This special cycle notifies external logic that all internal cache lines have been invalidated, and tells the external L2 cache (if present) that it should also invalidate its cache entries.