Chapter 13. Device Configuration


The Previous Chapter

Reset signalling and timing, along with actions taken by the system and devices during reset, are the primary topics discussed in the previous chapter. The chapter also discussed software initiated reset and why it's required. The process of determining the default speed and link width and the subsequent software tuning of bus speed and link width are also detailed.

This Chapter

HyperTransport uses PCI configuration. This chapter describes HyperTransport technology configuration for host bridges, tunnels, and end (cave) devices. These devices use the type 0 configuration header format, while HyperTransport-to-HyperTransport bridges and bridges between HyperTransport and other PCI compatible protocols (e.g. PCI and PCI-X) use the type 1 header format and are described separately in Chapter 16, entitled "HyperTransport Bridges," on page 407. Many aspects of HyperTransport device configuration are exactly the same as for generic PCI devices, although some header fields are used differently in HyperTransport, and some not at all. Devices also require at least one HyperTransport-specific advanced capability register block in addition to the basic PCI configuration space header fields.

The Next Chapter

The high speed signaling performed by HT devices is based on point-to-point differential signaling and source synchronous clocking. Details associated with link power requirements and the driver and receiver characteristics are discussed in the next chapter. Also, the characteristics of the system- related signals, including RESET#, PWROK, LDTSTOP#, and LDTREQ# are discussed.



HyperTransport System Architecture
HyperTransportв„ў System Architecture
ISBN: 0321168453
EAN: 2147483647
Year: 2003
Pages: 182

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