Transaction Examples: Introduction


The following section describes some transactions which might be seen in HyperTransport. Not all cases are covered, but the ones which are presented are intended to illustrate two important aspects of each transaction:

Packet Format And Optional Features

Most of the control packet variants have a number of fields used to enable optional features: isochronous vs. standard virtual channels, byte vs. dword data transfers, posted vs. non-posted channels, etc. In each of the examples, the key options are described; in some cases, certain packet fields don't apply to a particular request or response at all. Refer to Chapter 4, entitled "Packet Protocol," on page 59 for low level, bit-by-bit packet field descriptions.

General Sequence Of Events

Once the packet fields are determined, the next topic covered in the transaction examples is a general summary of events which must occur in the HyperTransport topology to perform the transaction. The description starts at the agent initiating an information or request control packet and follows it (and possibly a data packet) to the target; if there is a response required, this packet (and any data associated with it) is similarly followed from the target back to the original requester. Packet movement through HyperTransport involves aspects of topics described in more detail in other chapters, including flow control, packet ordering and routing, error handling, etc.

For each of the examples, assume the link interface CAD bus is eight bits in each direction. This simplifies the discussion of packet bytes moving across the connection ” each byte of packet content is sent in one bit time. The only difference, when link width is greater or less than 8 bits, is how the packet bytes are shifted out and received. For example, on a 2-bit interface each byte of packet content is shifted onto the link over 4 bit times. For an interface 32 bits wide, four bytes of packet content are sent in parallel with each other in each bit time.



HyperTransport System Architecture
HyperTransportв„ў System Architecture
ISBN: 0321168453
EAN: 2147483647
Year: 2003
Pages: 182

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