Chapter 7. Transaction Examples

The Previous Chapter

The previous chapter described the ordering rules which apply to packets associated with the three types of HyperTransport I/O traffic: PIO, DMA, and Peer-to-Peer. Depending on whether compatibility with the full producer-consumer ordering model used in PCI is required or relaxed ordering is permissible, attribute bits in request and response packets may be set or cleared. These bits are defined by the requester and are used by devices in the path to the target, and within the target, to enforce proper ordering. HyperTransport applies dedicated sets of ordering rules for upstream I/O traffic, downstream I/O traffic, and the special ordering required of host bridges and in double-hosted chains. Refer to Chapter 20, entitled "I/O Compatibility," on page 457 for a description of the additional ordering requirements when interfacing HyperTransport to other compatible protocols (e.g. PCI, PCI-X, and AGP).

This Chapter

In this chapter, examples are presented which apply the packet principles in the preceding chapters and includes more complex system transactions, not previously discussed. The examples include reads, posted and non-posted writes , and atomic read-modify-write.

The Next Chapter

HT uses an interrupt signaling scheme very similar to PCI's Message Signaled Interrupts. The next chapter defines how HT delivers interrupts to the Host Bridge via posted memory writes. This chapter also defines an End of Interrupt message and details the mechanism that HT uses for configuring and setting up interrupt transactions (which is different from the PCI-defined mechanisms).