Chapter 17. Double-Hosted Chains

The Previous Chapter

The previous chapter described the configuration of devices that use the HyperTransport technology type 1 configuration header for bridges. Such devices include HyperTransport-to-HyperTransport bridges and bridges to other PCI compatible protocols (e.g. HyperTransport-to-PCI or PCI-X). The basic architecture of a HyperTransport-to-HyperTransport bridge is reviewed and the configuration header fields are described. Differences in usage of bit fields by HyperTransport bridge interfaces vs. PCI bridge interfaces are emphasized . The format of PCI compatible bridge headers is formally defined in the PCI-to-PCI Bridge Architecture Specification, Revision 1.1 .

This Chapter

This chapter describes the features of the optional HyperTransport double-hosted chain topologies. Topics include the reasons behind sharing and non-sharing chains, PCI configuration space registers used to initialize the fabric for multiple hosts , and tunnel support for upstream and downstream packets moving in both directions.

The Next Chapter

HT provides a variety of mechanisms to support power management. These mechanisms include LDTSTOP#, LDTREQ#, STPCLK messages, and STOP_GRANT messages. While these mechanism are optional for HT devices, the specification requires this support for x86-based platforms. Note also that functions other than power management may make use of these signals and messages. This chapter discusses the strategy employed by HT for implementing power management and how a given platform can use these mechanisms to support power management.