Packet Routing: Shared Bus vs. Point-Point Topology

Routing information in a shared bus topology such as PCI or PCI-X is somewhat simpler than in a point-point topology such as HyperTransport.

Shared Bus Routing

Referring to the PCI/PCI-X shared bus example illustrated in Figure 11-1 on page 258, it should be clear that if a transaction appears on the shared bus, all devices "see it" and have an opportunity to decode the address and command and claim the cycle. Devices other than bridges have no responsibilities for routing information to their neighbors. Also note that arbitration on a shared bus is simple because a single arbiter can manage the entire bus. In PCI/PCI-X, the arbiter is typically in the bus Host Bridge; the arbiter considers requests from each master, then grants the bus to each in turn , hopefully applying a reasonable fairness algorithm.

Figure 11-1. Routing: Shared Bus vs. HyperTransport Point-Point

HyperTransport Point-Point Routing

In contrast to the shared bus approach, the HyperTransport topology distributes responsibility for routing and forwarding packets among all devices, with the exception of single-link end (cave) devices. For example, the tunnel peripheral device in Figure 11-1 on page 258 must observe a set of rules governing acceptance, forwarding, and rejection of packets moving both upstream and downstream. The end device in Figure 11-1 on page 258 is dependent on the tunnel to do this. Note that a benefit of a point-point bus is the elimination of shared bus arbitration. Packet transfer is subject only to flow control on each link.