Background and Introduction

First, a brief review of the essential elements of the high-speed link is provided including an introduction to the primary aspects of the electrical signaling environment.

Each link consists of two sets of uni-directional signals (see Figure 14-1) that support concurrent data transfers in each direction. HT achieves high performance by transferring data at a maximum clock frequency of 800MHz, coupled with the use source synchronous double data rate (DDR) clocking techniques. DDR clocking permits data transfer on both the rising and falling edges of each clock. HT also relies on low voltage swing differential signaling with on-die differential termination to facilitate the high-speed data rates and to improve noise immunity.

Figure 14-1. Link Signals

The following list reviews each of the differential high speed signals that is used when transferring data across the link.

• CAD (Command, Address and Data) ” Carries HyperTransport requests , responses, data packets, and other information across the link. CAD can be different widths in each direction depending on performance needs.

• CTL (Control) ” When asserted, CTL indicates that the CAD signals are carrying a control packet. When deasserted, CTL indicates that the CAD signals are carrying a data packet. There is one CTL signal for each data direction.

• CLK (Clock) ” This is the source synchronous clock used when transmitting CAD and CTL signals. Each byte of CAD has its own clock. Note that the CTL signal is clocked by the same clock used for CAD[7:0].

Because the link width is scalable, the number of source clocks used also varies. Table 14-1 on page 365 below lists the transmit signals that share the same source synchronous clock.

Table 14-1. Signal Group /Source Synchronous Clock Association

Signal Group	Source Synchronous Clock
CADOUT [7:0], CTLOUT	CLKOUT (0)
CADOUT [15:8]	CLKOUT (1)
CADOUT [23:16]	CLKOUT (2)
CADOUT [31:24]	CLKOUT (3)

The four system- related signals associated with each link are implemented as single-ended LVCMOS signals and as open drain wired-OR outputs to allow multiple sources to drive them. These signals include:

• PWROK (Power OK) ” Driven by system logic, this signal is a required input to each device. It may also be driven by HT devices in conjunction with RESET# to extend the reset time needed for their internal initialization.

• RESET# ” This signal is driven by system logic and is a required input to each HyperTransport device. It may also be driven by HT devices in conjunction with PWROK# to extend the reset time needed for their internal initialization.

• LDTSTOP# (Lighting Data Transfer Stop) ” Supports power management and other features that require a change of state on the links (e.g., it disables the link during power state transitions).

• LDTREQ# (Lightning Data Transfer Request) ” An output from HT devices that permits a device to request the links be re-enabled for normal operation.

The following sections describe the power requirements, electrical, and timing characteristics of both the differential and single-ended signals, as well as an overview of the testing environment.