| HP servers can be considered to employ either a Precision Architecture or Itanium architecture. HP's Precision Architecture utilizes PA-RISC processors that are now all 64-bit RISC processors. It has been some time since HP sold a 32-bit PA-RISC processor. Today's high-performance applications demand fast processing speeds and the ability to manipulate large data sets. Fast processing doesn't necessarily equate to hyper megahertz speeds; the current, latest PA-RISC processor operates at 875MHz. There are cost considerations as well as performance considerations why such a speed is chosen . Even though it may not be the quickest RISC processor on the market, purely on megahertz specification the PA-8700+ processor has proven to be an industry leader, with the PA-RISC Superdome server winning many benchmarking accolades when pitched against similar single-server solutions (see http://www.hp.com/products1/servers/scalableservers/superdome/performance.html for more details). RISC processors have been the cornerstone of the UNIX server arena for some time. The key technology differentials for a RISC processor can be summarized in Table 1-1 as follows : Table 1-1. Key Characteristics of a RISC Architecture | Fewer instructions (this is not a necessity of the architecture design) | Simple instructions are hard wired into the processor negating the need for microcode . | | Simple instructions executing in one clock cycle | Larger number of registers | | Only LOAD and STORE instructions can reference memory. | Traditionally can be run at slower clock speeds to achieve acceptable throughput | | Fixed length instructions | |
A 64-bit architecture offers an address space that most modern applications demand. In fact, HP doesn't utilize the entire 64-bits available to the architecture within HP-UX, because having 2 64 (=16 Exabyte) processes appears to be beyond the needs of even the most memory-hungry applications. The current PA-RISC servers can accommodate 64 processors and 256GB of RAM utilizing the PA-8700+ processor. In the near future, the PA-8800 processor will be able to run at speeds in excess of 1GHz and support a memory compliment of 512GB and beyond. The future looks secure for the PA-RISC processor. As always, processor designers are looking for new ways to make the processors work faster and more efficiently . With a close collaboration between HP and Intel, a new architecture has emerged that looks set to take the computer industry by storm . The architecture is known as EPIC (Explicitly Parallel Instruction Computing). This is not a new architecture but finds its roots in an architecture dating back to machines developed in the 1980s using a concept known as Very Long Instruction Word (VLIW). The key characteristics of a VLIW architecture can be summarized in Table 1-2: Table 1-2. Key Characteristics of a VLIW Architecture | Fewer instructions | Large number of registers to maximize memory performance | | Very high level of instruction level parallelism | Less reliance on sophisticated "branch management" circuitry on-chip as the instruction stream by nature should be highly "parallel-ized" | | Fixed length instructions | | | Multiple execution units to aid superscalar capabilities | |
The product of this collaboration is a range of processors known as Itanium. This was formally known as IA-64 to reflect the compatibility with and extension of the IA-32 architecture seen in traditional 32-bit PA-RISC processors. Itanium is said to be an instance of the EPIC architecture. A major driving force behind the need for a new processor architecture is an attempt to narrow the gap between processor speed and the speed of the underlying memory system. While processor speeds have been seen to gallop into the distance, most main memory solutions are still operating at or around 60 nanoseconds. Compare that to the operating speed of a lowly 500MHz processor of 2 nanoseconds. The designers of VLIW processors, such as Itanium2, are utilizing ever-cleverer compiler technology and multi-level high-speed cache in an attempt to keep the processor supplied with a constant instruction stream. The current crop of Itanium processors (Itanium2) is operating at 1.5GHz and supports a 512GB memory compliment. Like their PA-RISC cousins , the Itanium2- powered Integrity Superdome servers are smashing performance benchmarks wherever they go (see http://www.top500.org). The scheduling of tasks on the processor(s) is a job for the kernel. The kernel has at its disposal up to four basic schedulers to help with this task: the POSIX real-time scheduler, the HPUX real-time scheduler, the HPUX timesharing scheduler, and the PRM scheduler. Within each of these schedulers are techniques for extracting the most out of our applications. Each needs to be understood before being used. For example, if the POSIX real-time scheduler is used on a server running in a Serviceguard cluster, a compute-bound application could cause a server to TOC due to the Serviceguard daemons being locked out of the processor. As you can imagine, having servers crash because of a scheduling decision is not a good idea and highlights the need not only to be able to use an advanced technology, but also to understand it as well. What we have there is a classic trade-off between high availability and performance. Can we achieve both? Yes, we can, as long as we understand the impact that our decisions make. |
