Section B.2. The DS92LV16 Serial Link for Data Streaming


B.2. The DS92LV16 Serial Link for Data Streaming

As described in earlier chapters, the Impulse C stream is a means by which two Impulse C processes can communicate through a standard interface. For this project, which involves a relatively large array of processing elements (the FPGAs) communicating between different FPGA boards, it was necessary to implement an Impulse C-compatible stream that can communicate over DS92LV16 serial links. The hardware stream that was created for this application is not as general as the standard Impulse C stream, because limitations such as data width are imposed by the hardware. Nonetheless, for this application, the Impulse C stream provides a good abstraction for the kind of data movement required by the algorithm.

The serializer hardware allows a maximum of 16 bits to be sent during each clock cycle. Since it is also necessary to send control flags such as FIFO status, write enable, and end-of-stream signals in addition to the raw data, not all of the 16 transceiver bits are available for data transmission. Of the 16 bits, 3 are used for control flags, and the rest are available for data, with data widths of up to 13 bits. Another difference between this stream definition and the Impulse C stream is the need to initialize the serial link before using it. A handshaking scheme is implemented to ensure that both transceivers are locked to the serial data stream before allowing data transmission. The following sections discuss the details of the handshaking process as well as the specifics of data transmission.

Initializing the Serial Connection

The implementation uses a simple handshaking process to ensure that both the remote and local hardware transceivers are locked onto the serial data stream prior to proceeding with data transfer. Figure B-2 shows the control flow for the handshaking. The first step is sending out a synchronization pattern while waiting for the local transceiver to lock to the serial data stream. After being locked on for a period of a few tens of milliseconds (to allow for switch bounce effectsfor example, if a cable was pulled off and replaced), the state machine alternately sends out flags and the synchronization pattern for 240 clock cycles each. The synchronization pattern allows the remote DS92LV16 to lock onto the data stream if it has not done so already.

Figure B-2. Impulse C-to-serializer/deserializer handshaking state machine.


The SERDES must receive the synchronization pattern for 150 clock cycles to ensure synchronization with the serial data stream. Therefore, the slightly larger value of 240 clock cycles was chosen for the synchronization period to make sure the remote receiver can lock to the serial stream.

The transmitted flags indicate the status of the local state machine, allowing the remote state machine to know its state. If a valid flag response is received, the first acknowledge state is entered, which simply waits for the remote transceiver to reach the same state. When the remote state machine reaches the first acknowledge state, the local state machine progresses to the second acknowledge state. In the second acknowledge state, a sequence of flags is sent out for a period of time until it is determined that the remote state machine is also in this state, or until a timeout occurs. Upon leaving the second acknowledge state, the connected state is entered, signifying that both the remote and local transceivers are locked and data transmission can begin. If the local lock signal is ever lost, such as because the serial cable got disconnected, the state machine reverts to the initial state, and the handshaking process is repeated.



    Practical FPGA Programming in C
    Practical FPGA Programming in C
    ISBN: 0131543180
    EAN: 2147483647
    Year: 2005
    Pages: 208

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