Section B.3. Stream Interface State Machine Description


B.3. Stream Interface State Machine Description

While reading the following descriptions, refer to the state diagram shown in Figure B-2. The VHDL source code listings corresponding to these descriptions are found in Figure B-5 at the end of this chapter.

State: send_sync

In state send_sync, the sync_out bit is set high. This tells the transceiver to send a synchronization pattern allowing the remote transceiver to lock to the serial stream. The state machine remains in this state until the counter variable reaches 0x200000, signifying that the local transceiver has been locked to the serial stream for 26ms. This value was arbitrarily chosen, but it works with this particular hardware. After being locked for 26ms, state send_sync_240 is entered.

State: send_sync_240
State: send_flags_240

In state send_sync_240, the sync_out bit is held high to enable the sending of the synchronization pattern. The variable flag_cnt is incremented each clock cycle. When flag_cnt reaches 240, the state changes to send_flags_240 and flag_cnt is set to 0. In send_flags_240, the sync_out bit is cleared and a flag sequence is sent out instead of the synchronization pattern. In both of these states, the data received from the local transceiver is monitored. The counter variable is used to keep track of for how many clock cycles specific flags were received. If the counter reaches 0x000FFF in either of these two states, the local state machine advances to state send_ack1. However, if the local transceiver loses synchronization with the serial data stream in either state, the state machine reverts back to state send_sync.

State: send_ack1

State send_ack1 is used to let the remote state machine know that it has advanced beyond the previous two states. This is done by sending a new, different flag sequence corresponding to this state. The local state machine remains in this state until the remote state machine has reached either this state or an advanced state for 240 clock cycles, as determined by the value in flag_cnt. Upon receiving the appropriate flags for 240 clock cycles, state send_ack2 is entered.

State: send_ack2

Once this state is reached, both ends of the serial connection know that the opposite end has established a connection. This state is simply to allow the remote state machine to exit the send_ack1 state. Flags are sent out until it has been determined that the remote state machine has been in this same state for 240 clock cycles or until a timeout occurs. When either scenario happens, the connected state is entered.

State: connected

In the connected state, the link_established bit is held high, indicating to the other processes that the serial connection is available for their use. The data sent to the transceiver is set to data_to_transceiver, which is controlled by the data transmission logic. The state machine remains in this state unless the local transceiver loses synchronization with the serial data stream, in which case the send_sync state is entered and the handshaking process is repeated.



    Practical FPGA Programming in C
    Practical FPGA Programming in C
    ISBN: 0131543180
    EAN: 2147483647
    Year: 2005
    Pages: 208

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