2.5. Parallel IO Buses

2.5. Parallel I/O Buses

The bottleneck now shifted to I/O access and I/O bus speed. Multiple I/O devices in a server were located on one bus and were limited to one bus speed.

This limitation was solved by adding dual-peer and triple-peer I/O buses. This design was possible by adding more I/O controllers called bridges, as shown in Figure 2-5.

Figure 2-5. Parallel I/O bus architecture.

With this design, peripherals on any bus have independent access to the processors and memory. This design also allows I/O buses to operate at different speeds, separating the slow I/O from faster I/O. Buffers in the bridges allow I/O transfers to queue, reducing latency.

The key benefits of this design included the following:

• Twice the I/O bandwidth of single-bus systems 267MB/s (533MB/s) compared to 133MB/s (267MB/s)

• Support for more PCI devices than single-bus systems

• Balance of I/O workload and performance by placing high-usage peripherals (such as the graphics controller and disk controller) on separate buses