5.3 Class AB CMOS transconductor

5.3 Class AB CMOS transconductor

Ideally, a transconductor linearly converts an input voltage into an output current with both input and output ports presenting infinite impedance. Our transconductor must be implemented in standard digital CMOS and so we must find a solution which has the required high performance while satisfying the voltage headroom constraints imposed by the process.

5.3.1 Cell development

One promising approach which uses the PMOS/NMOS transistor pair proposed by Nauta [11] for mainly high-frequency filters and employed recently by Andreani [12] at lower frequencies is shown in Figure 5.10a. If the PMOS and NMOS transistors P and N have identical parameters (this is an unnecessary constraint but one which simplifies the description), then g_mp = g_mn = g_m and the overall transconductance of this single-ended cell is −G where G = 2 g_m. Biasing the input at the mid-rail voltage (V_dda/2) produces equal drain currents J in both P and N and the output current is zero. When the input voltage changes by v_in, the drain currents of N and P are unbalanced as given by

and a linearly related current, i_out = I_p − I_n = −Gv_in, flows at the output. This theoretical linearity occurs despite the square law relationships determining the individual currents as shown in normalised form in Figure 5.11. The transconductor is exceptionally efficient because it operates in class AB for peak output currents as high as i_out = 4J.

Figure 5.10: Class AB CMOS transconductors: (a) simple single-ended; (b) simple balanced; (c) fully differential

Figure 5.11: Normalised (J = 1, G = 1) behaviour of the class AB transconductor

One feature of this transconductor is that G is influenced by the bias current J which is strongly determined by the supply voltage, V_dda. This feature allows either the value of G or the frequency tuning of the filter to be simply controlled using control circuits like those described later. It also carries a penalty for power supply noise feedthrough. Assuming square-law saturated MOS behaviour, the transconductance is given by

where k = 0.5 μC_oxW/L. If now the value of V_dda is modulated by a signal v_d then G is also modulated

and the output current is given by

So, in addition to the wanted output signal, −Gv_in, there is an extraneous signal, kv_inv_d, which results in intermodulation of signals with supply noise. Consequently, great care must be taken when designing the V_dda control circuit so that both V_dd and V_ss noise is effectively suppressed.

Balanced transconductors (which are able to convert a balanced input voltage into a balanced output current) are highly desirable. In Gm-C filters, inversion of signals is frequently required and this can be achieved by simply crossing over signal pairs. A simple balanced arrangement may be formed from two of the single-ended transconductor cells as shown in Figure 5.10b, one converting the positive signal voltage and the other converting the negative signal voltage, and achieves a differential transconductance G_m = G/2. Unfortunately, if this simple arrangement is used in feedback networks, such as the gyrator loops occurring in a Gm-C filter, the circuits become unstable.

This can be resolved with a fully differential transconductor such as that shown in Figure 5.10c [11]. It comprises two main single-ended transconductors (−G) and a common-mode feedback network between the input ports. This employs four halfsize single-ended transconductors (−G/2, each using half-width transistors and half the bias current) coupled between the inputs of the main transconductors.

First, consider this transconductor under quiescent conditions, i.e. v⁺ _in = v⁻_in = 0, i.e. both inputs are at V_dda/2 and the output currents are zero. The current in each of the common-mode feedback MOSTs is J/2 and the feedback currents are i⁺_f = i⁻_f = 0

Next, consider the transconductor with purely differential input voltages, i.e. v⁺_in = v_dm/2 and v⁻_in = −v_dm/2 where v_dm is the differential mode input voltage. The feedback currents are again i⁺_f = i⁻_f = 0 because the half-size transconductor pairs generate equal and opposite currents that cancel. The voltages v⁺_in and v⁻_in are applied directly to the main transconductor inputs and a current of −v_dm G/2 flows at the outputs.

Finally, consider the transconductor with common-mode input currents, i_cm. These force the input voltages, v⁺_in and v⁻_in, until i⁺_f = i⁻_f = i_cm. This occurs when v⁺_in = v⁻_in = i_cm/G and this causes a common–mode output current i⁺_out = i⁻_out = −i_cm. So, while the transconductor has not rejected the common-mode input it is nevertheless stable.

One problem with this transconductor arises because of feedthrough from input to output via the gate–drain capacitances. Had these capacitances been reciprocal (i.e. C_gd = C_dg) then the balanced gyrators formed by the −G, + G loops in a Gm-C filter (see Figure 5.12) would have equal feedforward and feedback capacitances which produce no resultant feedthrough. Unfortunately, the capacitances of a MOS transistor in saturation are non-reciprocal [13] as shown in Figure 5.13. As a saturated MOS transistor is ‘pinched-off’ at its drain, voltage disturbances at the drain do not influence the channel charge and so C_gd ≈ 0. On the other hand, voltage disturbances at the gate directly influence the channel charge (to produce a change in the drain current) and so . In a gyrator loop, the strong feedforward via C_dg in transconductor −G (or + G) is not balanced by an equal feedback via C_gd in transconductor + G (or- G) and this can produce filter responses which peak at high frequency.

Figure 5.12: Gyrator loop of two transconductors with feedthrough capacitance

Figure 5.13: Capacitances of a MOS transistor in saturation

The solution to this is shown in Figure 5.14. The pMOS capacitors C_p are connected between each input and a source follower connected to each output. Voltage disturbances at the transconductor input produce feedforward via C_p but the capacitive current is routed harmlessly via the source follower to V_ss and the transconductor experiences no extra feedforward. However, voltage disturbances at the transconductor outputs do produce feedback via C_p. Clearly, C_p creates only capacitive feedback while the internal transconductors produce only feedforward. If we make , then the fully differential transconductor has reciprocal feedthrough capacitance. Now when the transconductors are connected as gyrators, the feedforward cancels the feedback and feedthrough is eliminated.

Figure 5.14: Transconductor with capacitive feedthrough equalisation

A further enhancement to the transconductor of Figure 5.10c which improves its common-mode rejection ratio is shown in Figure 5.15. The extra resistor R in the common-mode feedback network is given the value R = 1/G. With purely commonmode input currents, i_cm, the input voltages, v⁺_in and v⁻_in, adjust until i⁺_f = i⁻_f = i_cm as before. This occurs when v⁺_in = v⁻_in = i_cm/G but now i_cm flows via resistor R to produce an extra voltage drop of −i_cm/G. Consequently, the transconductor input voltage stays at its quiescent value (V_dda/2) and the common-mode input is rejected. With purely differential signals, i⁺_f = i⁻_f = 0 as before and there is no voltage drop across R.

Figure 5.15: Transconductor with improved common-mode rejection

So, in a Gm-C filter, we would use the transconductor with feedthrough equalisation (Figure 5.14) in all gyrator loops but we may use the transconductor with improved common-mode rejection ratio (Figure 5.15) at the filter terminations.

5.3.2 Frequency tuning

One feature of the class AB transconductor cells is their sensitivity to the supply voltage. They are only practicable when operated from a regulated supply and this may be integrated with a coarse automatic frequency tuning scheme as shown in Figure 5.16a. Greater precision would be possible with a phase-locked loop [14] but as the required tuning accuracy was only 6 per cent the simpler arrangement described here was adopted to save power consumption and chip area. The arrangement uses a control loop comprising a skewed ‘diode-connected’ transconductor −G₀ which generates a quiescent voltage which is offset from that of the reference transconductor, a parallel arrangement of the reference transconductor −G and switched capacitor C, an integrator comprising −G_int and C_int, a digital inverter and a charge pump Q_pump for regulating the V_dda0 supply. In operation, the reference transconductor and switched capacitor supply the integrator with opposite polarity currents, i_g and i_c, which are integrated and amplified and then used to control the charge pump. With the switched capacitor set to the value G/F_ck the currents sum to zero and the loop stabilises with the value of V_dda0 required to achieve the desired time-constant. When the transconductor or capacitor have non-typical values, V_dda0 adjusts to change the transconductance value to restore the time constant to its nominal value. Necessarily, the loop regulates with a ripple on V_dda0 and so the supply voltage V_dda used by the filter is lowpass filtered by R_g and C_g. With the source follower regulating transistors SF₀ and SF scaled to produce the same V_gs, the value of V_dda tracks closely that of V_dda0 and the filter's transconductors will closely track the control loop's reference transconductor. The decoupling capacitors C_s0, C_g0, C_s and C_g were all nMOS oxide capacitors connected to minimise their gate voltages. They also serve the purpose of transmitting any substrate interference onto the V_dda rail. With near equal interference on both V_ss and V_dda rails very little signal is coupled into the filter.

Figure 5.16: Combined tuning and supply regulator arrangement

The charge pump [15] is shown in Figure 5.16b and operates when its enable input, e_n, is high and charge is pumped into the load capacitance via the pMOS switch S to produce a voltage at Q_out which can rise above the V_dd supply voltage. The resistor R_L acts as a pull-up resistor when Q_out is low during start-up and as a pull-down resistor when Q_out is high and this allows the loop to stabilise satisfactorily.

The tuning loop was designed for a clock frequency of 26 MHz. The transconductor −G₀ produces an offset voltage of about 80 mV. The integrator transconductor −G_int was the same as the reference transconductor −G but 20 times larger and so produced the same quiescent input voltage. The capacitors C₀ and C_int were each about 20 times larger than the pMOS switched capacitor C, the value of which was adjusted, with typical processing and temperature, until the stabilised value of V_dda had the value needed to tune the filter to its nominal response. The cut-off frequency of the lowpass filter formed by R_g and C_g was made sufficiently low to reduce the ripple on V_dda to less than 0.1 mV.