5.4 Filter design

5.4 Filter design

The balanced channel filter (Figure 5.7) was implemented in a 2.5 V, 0.25 μm, standard CMOS process. It employed feedthrough-equalised fully differential transconductors operating from a supply voltage (V_dd) of 2 V and an internal analogue supply (V_dda) of 1.58 V. The I - and Q-channel transconductors all had differential transconductance of 20 μS (G = 40 μS) while the cross-branch transconductors were of the same design but with their transistor widths and currents scaled appropriately. This value of transconductance was necessary to achieve the required signal-to-noise ratio. The common-mode feedback networks (not shown for simplicity) were connected across each capacitor and scaled according to the total transconductance that they served. The floating capacitors were made from antiparallel pairs of pMOS transistors operated in accumulation.

The transistor level design of the 20 μS differential reference transconductor (Figure 5.14) started with the sizing of the nMOS and pMOS transistors to give equal transconductances of 20 μS while having a sufficiently low gate-overdrive voltage to ensure saturated operation with drain currents up to four times the quiescent current. For this design, the areas of the transistors were made large enough to give sufficient matchingforthedesiredimagerejectionbutnotsolargethattheirparasiticcapacitance dominated the nodal capacitances required by the filter. The quiescent gate overdrive voltage was set to V_gt ≤ V_t/2 ≈ 0.25 V and, for the chosen process, this required the transistor sizing shown in Figure 5.17.

Figure 5.17: Transistor level design of 20 μS transconductor half circuit

The circuit operates with V_dda ≈ 3 V_t = 1.58 V and transconductor drain currents of J = 2.45 μA. The calculated mismatch of the I - and Q-channel reference transconductors gave a transconductance standard deviation of σ ≈ 0.5 per cent (the cross-branch transconductors will be better matched). The neutralisation network was designed with the appropriate feedback capacitance, 0.4(C_gsp + C_gsn), and its source follower was biased sufficiently (0.35 μA) to keep it out of cut-off under large-signal, high-frequency conditions. The total current drawn by the differential reference transconductor including four half-sized common-mode feedback transconductors was 10.5 μA.

Next, the floating capacitors were designed. This was achieved by first sizing the MOS capacitors to give half the single-ended values defined in Table 5.1 and then including them with the designed transconductors in a transistor-level simulation model of the whole filter. Simulating this filter would produce a distorted amplitude response because each capacitor is loaded by the transconductor parasitic capacitances. So, each of the floating capacitors was trimmed to give the design value. Using the arrangement shown in Figure 5.18 with an AC voltage source connected across the selected capacitor (C₃ in this case) in the I-channel and short circuits across its neighbouring capacitors (C₂ and C₄) and across the corresponding capacitor (C₃) in the Q-channel, the selected capacitor together with its immediate parasitics are isolated from the rest of the filter network. The currents flowing in the short circuits allow extraction of the nodal capacitance (C₃ = imag(I₁/2πf)) and the surrounding transconductances (G = real(I₂) and G₃₃ = real(I₃)) for subsequent trimming to the design values. The same trimming procedure was adopted for each capacitor in turn. Typically, this trimming was only a few per cent of the capacitor value.

Figure 5.18: Filter arrangement for trimming nodal capacitances