The parallel port, sometimes called a printer port, was originally designed to connect a printer to the computer. Over the years, many other devices, such as scanners, removal drives, and copy protection devices, have been connected to PCs via parallel ports. In today's PCs, this port has eight bidirectional data lines, four bidirectional control lines, and five status input lines, and they are accessed through a DB-25 female connector. Since its inception, the parallel port has evolved into four types:
The IEEE standard 1284, "IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers," defines these four types and is summarized in this document:
Other online documentation fully explains the similarities and differences between these types and are as follows:
Project Trailblazer requires six inputs and four outputs. Using the online documentation, the engineers determined the bidirectional SPP type of port will suffice. The port does not need to control a high-speed printer just some simple slow-speed inputs and outputs.
SPP hardware is usually port I/O mapped to the x86 ISA bus (that is, the port isn't memory mapped) at I/O base address 0x378. By using the motherboard BIOS, you can change this address and port type. For this chapter, make sure that your PC's BIOS configures LPT1 as an SPP type at the base address 0x378. The three SPP software registers data, status, and control exist at the base address, base address + 1, and base address +2 (that is, 0x378, 0x379, and 0x37A). Figure 7.1 shows these software registers, their bit definitions, and the hardware connections to the DB-25 parallel port connector.
Figure 7.1. PC parallel port connection to software registers. The highlighted registers to DB-25 port connections are electrically inverted.
The control register contains two additional bits that are not shown in Figure 7.1. Control bit 5, bidirectional port enable, configures the data bus hardware for input. Control bit 4, IRQ via Ack Line enable, configures the port hardware to generate an interrupt on a low-to-high transition of the Ack line, DB-25 pin 10. Parallel port interrupts are not required for Project Trailblazer acquisition or control. The engineers built a parallel port software development test fixture, shown in Figure 7.2, with switches connected to inputs and LEDs connected to outputs.
Figure 7.2. The parallel port software development test fixture.
Some PC parallel ports don't actively drive their data and control signals when at Logic Level 1. These open collector/drain signals are pulled high with a resistor located inside the PC. The value of this resistor, which you don't know and can't control, affects the LED's brightness. If you are experiencing problems using LEDs to debug your parallel port programs, you should use a voltmeter or logic probe instead. Also, keep in mind that certain control and status signals are inverted in hardware.
An SPP has the six inputs and four outputs Project Trailblazer needs. However, some Silverjack locations will require eight outputs, so the parallel port alone doesn't meet the lift monitoring and snow-making I/O requirements. The engineers designed an interface circuit, shown in Figure 7.3, that connects the PC parallel port to two off-the-shelf Grayhill I/O module boards (www.grayhill.com). This interface circuit consists of an input path that uses an input buffer 74HC244, connected to an Input module rack and an output path that uses an output latch, 74HC533, connected to an output module rack. Both the buffer and the latch data busses connect to the parallel port's data bidirectional data signals, D7 D0. The input buffer's enable (/OE), the output latch's output enable (/OE) and latch enable (/LE) connect to parallel port's control lines. In an output operation, one that turns on or off an AC output module, a byte is placed on the parallel port's data bus and the OUTPUT_LATCH signal is asserted. The latch transfers the data byte from the signal lines D7 D0 to its output signals that in turn drives the output module board. The board's AC output modules turn on or off corresponding to the bit pattern sent during the output operation. In an input operation, the parallel port's bidirectional data bus, now configured for input, reads the D7 D0 signal lines driven by the input buffer. When the INPUT_ENABLE signal is asserted, the input buffer transfers the eight signals from the Input module rack and drives the D7 D0 signal lines accordingly. Upon CPU reset, the parallel port control register contains 0s that results in the OUTPUT_ENABLE signal to be not asserted. This disables the latch output, turning off all output modules. Software using this interface circuit will perform input and output operations by accessing the parallel port's data and control registers. Datasheets for the 74HC244 and 74HC533 are available from Texas Instruments (www.ti.com).
Figure 7.3. Project Trailblazer PC parallel port acquisition and control circuit.
When you are designing control circuitry, pay close attention to the hardware's startup conditions. You don't want the interface circuitry turning on or off field devices by itself, before your control software starts executing. You should look at register reset values and determine their effect on your logic circuitry. Then add pull-up or pull-down resistors to force your interface logic into a known state. When the control software starts execution, it can take over and control your external devices.