4.4. Processes Streams Signals, and Memory
At the heart of the Impulse C programming model are processes and streams. You saw examples of both of these elements in the preceding HelloFPGA example.
Processes are independently synchronized, concurrently operating segments of your application. Processes are written using standard C (subject to the limitations of the target processing element, whether hardware or software). They perform the work of your application by accepting data, performing computations, and generating outputs.
The data processed by your application flows from process to process by means of streams, or in some cases by means of messages sent on special channels called signals and/or via shared memories. Streams represent one-way channels of communication between concurrent processes and are self-synchronizing with respect to the processes by virtue of buffering. The characteristics of a given stream (its width and depth) are specified at the time a stream is created in your application using co_stream_create.
As you saw in the "Hello FPGA" example, the implementation of a process is defined by a user-defined C procedure called the process run function. When compiling an application for a target platform, each process is classified as a software process or a hardware process based on its location specified in the configuration subroutine. The possible locations are defined by the target platform.
A software process is constrained only by the limitations of the target processor (whether a common RISC, a custom DSP processor, or a custom processor core), while a hardware process is typically more constrained. A process written for an FPGA, for example, must be written using a somewhat narrowly defined subset of the C language to meet the constraints of the Impulse C hardware compiler. In addition to standard C expressions, predefined functions that perform stream or signal operations may be referenced in a software or hardware process.
The Impulse C compiler generates synthesis-compatible hardware descriptions for one or more FPGAs as well as a set of communicating processes (in the form of C code compatible with the target cross-compiler) to be implemented on conventional processors. The compiler is capable of scheduling and pipelining stream operations and other computations (within loops, for example) so that the generated hardware descriptions take advantage of parallelism within the target hardware itself.