10 BaseT:

IEEE 802.3 specification for 10-Megabit Ethernet implementation on twisted-pair wiring.

100 BaseT:

IEEE 802.3 specification for 100-Megabit Ethernet using level-5 UTP.

10G Ethernet:

10-Gigabit Ethernet supports the data rate of 10 Gbps and supports the features of the preceding Ethernet standards. The potential applications for 10-Gigabit Ethernet are Local Area Network (LAN), Metropolitan Area Network (MAN), and Wide Area Network (WAN).


The A TM A daptation L ayer is a service-dependent sublayer of DLL (Data Link Layer) that transfers data from various applications to the ATM layer using 48-byte ATM payload formats. ITU-T has recommended four types of AAL: AAL1, AAL2, AAL3/4, and AAL5.


Layer 1 of AAL is used for connection-oriented, delay-sensitive applications with a constant data rate, such as uncompressed video transfer.


Layer 2 of AAL is used for connection-oriented applications with variable data rate, such as voice transfer.


An A nalog- t o- D igital C onverter converts analog signals to digital signals using sampling and quantization techniques.


A daptive D ifferential P ulse C ode M odulation is a speech-compression technique that converts the analog voice signals to high-quality digital signals that can be transferred over 32-Kbps digital channels.


An ITU-T standard for Europe to convert analog data to digital data using the Pulse Code Modulation (PCM) algorithm. North America and Japan use the -Law standard.


An A pplication -S pecific I ntegrated C ircuit is a chip that is designed to satisfy a specific application's requirement.


A synchronous T ransfer M ode is a broadband transmission system that is based on small, uniform packets and is widely used in LANs and WANs.


A utomatic T est P attern G eneration provides a set of test vectors to identify all the faults in a circuit.


B all G rid A rray is a packaging methodology that reduces the area so more functions can be integrated on a single space. This packaging method provides higher performance due to the short distance that exists between the chips and solder balls. BGA chips are usually used on mobile applications since they are small and occupy less board area.


B uilt -I n S elf T est is a verification technique that allows a circuit, or portions of a circuit, to test itself and identify the faults. An output signal is sent when a fault is detected .

Boundary Scan:

Boundary scan is a testing methodology that allows the boundary pins of a JTAG-compatible circuit to be tested using software control.


C ode E xcited L inear P rediction is a voice-compression algorithm that is used for low bit-rate encoding/decoding. ITU standards for CELP are: G.728, G.729, and G.723.1.


Co der /dec oder is a compressor/decompressor device that converts specific types of analog data to digital data and vice versa. The analog data could be audio, speech, or video.


A C ompact P eripheral C omponent I nterconnect or compact PCI is a high-performance interconnect bus based on PCI standards, which can support 8 PCI slots on a single bus.


A D igital - to -A nalog C onverter is a device that converts digital information to analog voltage levels. One example is converting digital information from a CD to analog audio signals.


D esign F or T est is a chip-design technique that incorporates testing into a design from the very beginning of the design process to reduce the test-generation complexity at later stages.


D ual I n-line P ackage is a packaging method that uses two parallel rows of pins. Most DIP devices have 14 to 16 pins.


D ata L ink L ayer is the second layer in OSI model and defines how data moves to or from physical media to upper layers . It also provides error detection and flow control. DLL contains two sublayers : Media Access Control (MAC) and Logical Link Control (LLC).


D irect M emory A ccess is a data-transfer method that allows information to be transferred between several memories or other peripheral devices without the need to go through the CPU each time. DMA-based devices have faster data transfer compared to devices that require data to pass through the main CPU.


D esign R ule C heck is a process of checking the final semiconductor layout against a set of physical design rules. These rules ensure that the design will not fail due to short circuits or process faults.


A D igital S ignal P rocessor is a specialized processor used for analyzing digital signal-processing algorithms such as voice processing and compression.


D ual- T one M ulti F requency is a method used for voice processing and for use of two simultaneous tones such as in touchtone.


D evice U nder T est is the integrated circuit or part of the circuit that is of interest to the designer for testing.


E lectronic D esign A utomation tools are special software tools that are used to design and verify integrated circuits and systems.


E lectronic D esign I nterchange F ormat is an industry standard format for transferring and interchanging design data. EDIF files can be created from a design schematic, VHDL, or Verilog code that has been processed with through synthesis tools.


E lectrical R ule C hecking is the process whereby circuit designers check the electrical rules provided by ASIC vendors . Examples of ERC violation are open input, short circuit, NMOS connected to Vdd, and PMOS connected to Gnd.


Ethernet is a LAN transmission standard that uses the Collision Sense Multiple Access with Collision Detection (CSMA/CD) method. Ethernet is similar to IEEE 802.3 standard.


F irst -I n F irst -O ut is a buffer where data is processed in the order they were received. It is the opposite of a Last-In First-Out (LIFO) data structure.


A F inite S tate M achine is a useful method in digital design and is a function that maps a set of input events to their matching output events.


An ITU Pulse Code Modulation (PCM) standard for voice encoding/decoding at 48 to 64Kbps. It is a specification for A-Law/-Law coding.


An ITU standard for compression/ decompression of speech and audio signals with very low bit rates such as 5.3 and 6.3Kbps. The lower bit rate is CELP and provides more flexibility for designers while the higher bit rate has better quality and is based on Multipulse Maximum Likelihood Quantization (ML-MLQ) technology.


An ITU standard for ADPCM voice compression from a 64-Kbps A-law /-law channel to 40-, 32-, 24-, or 16-kbps channels.


An ITU standard for low-delay CELP voice compression.


An ITU standard for CELP voice compression at 8Kbps.


A point at a network that provides an entrance to another network and transfers packets from one network to another on Internet. Gateway is used in applications that route information from one network to another like packet switched networks.


GDSII is a binary file format that is used to transfer the layout circuit-design information.


H.100 is a telephony bus, such as ribbon cable bus, and is used to transfer voice over a Compact Peripheral Component Interconnect (CPCI).


H.110 is derived from H.100 and uses a Time-Division-Multiplexing (TDM) bus for telephony applications such as VoIP.


H ierarchical L ogic B locks are used in hierarchical design methodology and are blocks that can be independently laid out as hard macros.


The IEEE LAN standard which has different physical-layer specifications that define Ethernet, for example 10Base2, 10Base5, 10BaseF, 10BaseT, and 10Broad36. Various specifications, such as 100BaseT and 100BaseT4, are available for fast Ethernet.


An I nterface L ogic M odel improves chip-level timing-analysis performance mainly by reducing the size of the netlist. ILMs are used for static timing analysis with Synopsys Primetime. These have replaced the traditional STAMP models.


I ntellectual P roperty blocks are predesigned and verified blocks of logic that can be reused for multiple designs.


I nternet P rotocol provides features such as addressing, security, and type of service specification.


I nternational T elecommunication U nion is the organization that sets the international telecommunication standards.


A sector in ITU, it is responsible for standardization of worldwide telecommunications.


The J oint T est A ction G roup is an IEEE standard that controls the pins of compliant devices on a Printed Circuit Board (PCB) to ensure the board-level continuity.


L ayout V ersus S chematic is a method that compares the layout netlist to a schematic netlist to ensure that the layout matches the schematic.


M edia A ccess C ontrol is an IEEE specification for the lower half of DLL that defines the access-control protocols in an OSI model.


A MicroNetwork is a heterogeneous integrated network that unifies, decouples, and manages all of the communication between processors, memories, and input/output devices on an SOC.


A M edia I ndependent I nterface is a standard in Ethernet devices that interconnects the MAC sublayer and physical layer (PHY) despite the difference in media.


The M oving P icture E xperts G roup is a video-compression standard intended to reduce the storage requirements for full-motion video. MPEG includes several standards such as MPEG-1, MPEG-2, and MPEG-4. MPEG-1 provides CD-ROM-quality storage of video; MPEG-2 is used for Set-Top Boxes (STB), DVDs, and HDTVs; and MPEG-4 is used for seamless transfer of audio/video information over Internet and wireless channels.

m -Law:

An ITU-T standard for North America and Japan to convert analog data to digital data using PCM algorithm. Europe follows the A-Law standard.


M ulti V endor I ntegration P rotocol is a subset of the H.100 bus standard and is used for transferring data between switching and telephony processing boards on a PC.


O n -C hip B uses are used on complex ASICs and SOCs. System buses such as ARM AHB or MIPS system bus and peripheral buses such as PCI bus or ARM APB bus are examples of OCBs.


O pen C ore P rotocol is a core -centric protocol that is a bus-independent, high-performance, and configurable interconnect between various IP cores and on-chip communication subsystems. OCP is a functional superset of the VSI Alliance virtual-component-interface (VCI) specification (see Appendix B).


O ptical Internetworking F orum is a worldwide nonprofit organization that promotes development of products and services for optical internetworks.


O pen S ystems I nterconnection defines a reference model on how data should be transferred between two points in telecommunication networks. It contains seven layers: Physical, Data Link, Network, Transport, Session, Presentation, and Application.


Packets are small pieces of data of a fixed size that transfer data over networks. Packets usually contain header information and payload data. The header information provides the information on origin, destination, and synchronization. The payload provides the data.


A P eripheral C omponent I nterconnect is a local bus standard designed by Intel for PCs that provides high-speed connection between PCs and several peripheral devices.


P ulse C ode M odulation is a method for converting and transmitting analog signals commonly used by telephone companies. In this method analog signals are sampled at specific intervals to generate pulses , which are coded to represent the original analog signal.


A P in G rid A rray is a type of integrated circuit socket used for chips that have many pins since the connecting pins are at the bottom of the chip in squares with separation of only 0.1 inch in each direction.


P hase L ocked L oops are used for reduction of on-chip clock latency, synchronization of clocks between different ASICs, frequency synthesis, and clock-frequency multiplications.


A P ublic S witched T elephone N etwork is a worldwide voice telephone network.


Q uad F lat P ack is a surface-mount-technology (SMT) package for chips and is rectangular or squared with lead on all four sides.


R educed M edia- I ndependent I nterface is used in 10M and 100M Ethernet which offers faster transmission to MII with lower pin count.


A S ignal C omputing S ystem A rchitecture transmits information on a computer telephony system for multiple client applications.


A S tandard D elay F ormat is a standard format in the electronic industry for defining place and route delays in a design.


S erdes-to- F ramer I nterface Level 4 is an OIF standard that is optimized for pure data transfer and describes the data transfer with clock rates at the actual line rates.


S erdes-to- F ramer I nterface Level 5 is an OIF standard for 40-Gbps packet and cell transfer in applications such as Packet-over SONET/SDH.


SiliconBackplane is an example of a MicroNetwork which is licensed by Sonics, Inc. (see Section 1.3).


A S ystem O n a C hip is a system on an IC that integrates software and hardware intellectual property using more than one design methodology for the purpose of defining the functionality and behavior of the proposed system.


A S mall O utline P ackage is a type of packaging that has two rows of pins closely spaced with each other.


S ystem P acket I nterface Level 4 P hase 2 is a 10 Gbps electrical interface between the physical and data-link layers for SONET/SDH systems with independent transmit and receive interface.


S tatic T iming A nalysis is a static verification method that verifies the delays within a device. It is capable of verifying every path and can detect serious problems such as glitches on the clock, violated setup and hole times, slow paths, and excessive clock skew.


STAMP models are static timing models for complex blocks, such as DSPs and RAMs. STAMP models are created by core or technology vendors who provide database (.db) files for their customers as their timing models.


A S et T op B ox is used to receive and decode the digital TV signals from cable or satellite for digital home entertainment systems.


A T es t A ccess P ort consists of four pins defined by the IEEE1149.1 standard and provides boundary scan and other test interfaces for a circuit. These pins are TCK, TMS, TDI, and TDO.


T urn A round T ime. This term is frequently used in the semiconductor industry for the time it takes semiconductor vendors to make an ASIC prototype and a working part.


T ransfer C ontrol P rotocol is a transfer-layer protocol that provides retransmission sequencing for a reliable, connection-oriented transmission between two networks.


T ransmission C ontrol P rotocol/ I nternet P rotocol is a set of standards for network communications between multiple applications such as computers connected to networks.


T ime D ivision M ultiplexing is a technology that transmits multiple channels of information, such as voice, video, and data, over a single transmission path.


T ransmitting S ubscriber I dentification is a signal that shows the identification of the transmitting terminal.


U ser D atagram P rotocol is a network protocol for connectionless and unreliable transmissions that is used for exchange of replies between networks.


A U niversal S erial B us is a plug-and-play external interface between a computer and external peripherals using a bidirectional cable.


The U niversal T est and O peration P HY I nterface for A TM is an electrical interface for transmission of information on devices connecting to an ATM network.


The V irtual C omponent I nterface is a standard for bus architecture defined by VSIA for intellectual property interactions.


A Vo ice Coder is a speech/voice compressor/decompressor system that converts analog speech to digital signals and vice versa.


V oice O ver I nternet P rotocol is a technology that is used to transmit voice over digital networks on Internet with high quality and low cost.


V oice O ver N etwork is a method that uses packetized voice data for transmission over a network in Internet telephony technology.


V irtual S ocket I nterface A lliance is an organization that promotes standards to design SOCs with reusable intellectual properties.


W ide A rea N etwork is a system that connects LANs together over a long-distance medium.


A W ire L oad M odel relates a net's estimated length to estimated capacitance and resistance in a synthesis tool to provide an approximation of wire delays.


X ilinx N etlist F ormat was developed by Xilinx as a hardware-description language. XNF can be converted to other hardware-description languages such as Verilog.


From ASICs to SOCs. A Practical Approach
From ASICs to SOCs: A Practical Approach
ISBN: 0130338575
EAN: 2147483647
Year: 2003
Pages: 61

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