The goal of this section is to summarize the tips and guidelines for low-power design of ASICs and SOCs.
The most effective power-optimization techniques are the higher level ones. These are algorithmic and architectural optimization techniques.
Use low-power process and libraries. There are low-power standard cell libraries for 0.18 µm such as Xemics CooLib. (Refer to reference 16 for more information.) The low-power libraries should be used in conjunction with a low-power process that is available from most ASIC vendors .
Decrease the dynamic power by reducing all of the terms in the fundamental equation of power:
Apply the following for your supply voltages:
Lower the supply voltage for the entire chip when possible.
Use low-supply voltage for noncritical paths and high-supply voltage for components on critical paths.
Gate your clocks and high-activity signals whenever possible to prevent excessive switching activity in synchronous designs.
Reduce the power consumed in memory blocks/cores using the following approaches:
Minimize the number of accesses to main memory by having more code in cache.
Split large memories to smaller modules; for example, a 256k x 32 RAM can be split into two 128k x 32 RAMs.
Segment memories with individual clocks and put each segment in sleep mode when idle.
Minimize the number of transitions in high-activity bus interconnects using the following methods :
Partition a wide bus to multiple narrow buses since the bus width is directly related to power dissipation.
Use bus-encoding techniques such as gray coding, bus inverting, and partial bus inverting.
Use power management techniques to shut down or minimize the switching activities of certain blocks/cores in your SOC (i.e., put them in sleep mode). This is more effective through software solutions.
EDA power estimation and power-optimization tools should be used in all design abstraction levels. However, these tools are more effective early on at the algorithm or architecture phases of a design.