5.6 Summary


In this chapter, sources of power dissipation in CMOS devices were discussed.

The fundamental power equation


is the basis for all power reduction techniques. Each term in the equation can contribute to power savings.

Several methods of power optimization at different levels of design abstraction for ASICs and SOCs were explained. These techniques are:

  • Algorithm-level optimization

  • Architecture-level optimization

  • RT-level optimization

  • Gate-level optimization

In addition to power-optimization techniques, the simulation-based power-estimation method was discussed. Low-power EDA tools for predicting power at different levels of design abstraction were covered. Detailed information about some of the popular low-power design (estimation and optimization) tools is available in Appendix A.

Tips and guidelines for low-power designs were also covered.


From ASICs to SOCs. A Practical Approach
From ASICs to SOCs: A Practical Approach
ISBN: 0130338575
EAN: 2147483647
Year: 2003
Pages: 61

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