1.3 Intellectual Property

   

In today's rapidly growing IC technology, the number of gates per chip can reach several millions, exceeding Moore's law: "The capacity of electronic circuits doubles every 18 months." To overcome the design gap generated by such fast-growing capacity and lack of available manpower, reuse of the existing designs becomes a vital concept in design methodology. IC designers typically use predesigned modules to avoid reinventing the wheel for every new product. Utilizing the predesigned modules accelerates the development of new products to meet today's time-to-market challenges. By practicing design-reuse techniques ”that is, using blocks that have been designed, verified , and used previously ”various blocks of a large ASIC/SOC can be assembled quite rapidly. Another advantage of reusing existing blocks is to reduce the possibility of failure based on design and verification of a block for the first time. These predesigned modules are commonly called Intellectual Property (IP) cores or Virtual Components (VC).

Designing an IP block generally requires greater effort and higher cost. However, due to its reusable architecture, once an IP is designed and verified, its reuse in future designs saves significant time and effort in the long run. Designers can either outsource these reusable blocks from third-party IP vendors or design them inhouse. Figure 1.3 represents an approximation of the amount of resources used in several designs with and without utilizing the design-reuse techniques.

Figure 1.3. Resources versus Number of Uses

graphics/01fig03.gif

As shown in Figure 1.3, the time and cost to design the first reusable block are higher than those for the design without reusability. However, as the number of usages increases , the time-saving and cost-saving benefits become apparent.

Licensing the IP cores from IP provider companies has become more popular in the electronic industry than designing inhouse reusable blocks for the following reasons:

  1. Lack of expertise in designing application-specific reusable building blocks.

  2. Savings in time and cost to produce more complex designs when using third-party IP cores.

  3. Ease of integration for available IP cores into more complicated systems.

  4. Commercially available IP cores are preverified and reduce the design risk.

  5. Significant improvement to the product design cycle.

Intellectual Property Categories

To provide various levels of flexibility for reuse and optimization, IP cores are classified into three distinct categories: hard, soft, and firm.

Hard IP cores consist of hard layouts using particular physical design libraries and are delivered in masked-level designed blocks (GDSII format). These cores offer optimized implementation and the highest performance for their chosen physical library. The integration of hard IP cores is quite simple and the core can be dropped into an SOC physical design with minor integration effort. However, hard cores are technology dependent and provide minimum flexibility and portability in reconfiguration and integration across multiple designs and technologies.

Soft IP cores are delivered as RTL VHDL/Verilog code to provide functional descriptions of IPs. These cores offer maximum flexibility and reconfigurability to match the requirements of a specific design application. Although soft cores provide the maximum flexibility for changing their features, they must be synthesized , optimized, and verified by their user before integration into designs. Some of these tasks could be performed by IP providers; however, it's not possible for the provider to support all the potential libraries. Therefore, the quality of a soft IP is highly dependent on the effort needed in the IP integration stage of SOC design.

Firm IP cores bring the best of both worlds and balance the high performance and optimization properties of hard IPs with the flexibility of soft IPs. These cores are delivered in the form of targeted netlists to specific physical libraries after going through synthesis without performing the physical layout. Figure 1.4 represents the role of firm IP cores in ASIC design flow.

Figure 1.4. ASIC Design Flow

graphics/01fig04.gif

In Figure 1.4, the tasks in shaded boxes can be covered by Firm IP and as a result accelerate the design flow. Table 1.1 provides a brief comparison of different IP formats.

Table 1.2 provides a collection of some of the deliverable items for different IP formats.

Table 1.1. Comparison of Different Intellectual Property Formats

IP Format

Representation

Optimization

Technology

Reusability

Hard

GDSII

Very High

Technology Dependent

Low

Soft

RTL

Low

Technology Independent

Very High

Firm

Targeted Netlist

High

Technology Generic

High

Guidelines for Outsourcing IP

Although licensing IP can greatly enhance project design cycles, it can also hurt project schedules if the following are not carefully considered when selecting an IP vendor.

  • Outsource IPs from a well-known IP provider with large customer base and great track record. Customer testimonials of integrating a specific IP from a third-party vendor represent the best way of ensuring that the IP works in the integration process.

    Table 1.2. Some of the Deliverables for Various IP Formats

    Deliverables

    Hard IP

    Soft IP

    Firm IP

    HDL RTL code

     

    ¢

     

    HDL targeted netlist

       

    ¢

    GDSII file

    ¢

       

    Functional verification testbenches

    ¢

    ¢

    ¢

    Bus functional models

    ¢

    ¢

    ¢

    Floor planning models

    ¢

       

    Synthesis and timing models

    ¢

    ¢

    ¢

    Full documentation

    ¢

    ¢

    ¢

  • Evaluate the IP functionality using demos and executable models before purchasing. Hardware demonstrations by IP providers are another way of ensuring that IP blocks are functional in silicon. Access to executable models allows you to change different parameters and make sure the IP provides functional results that you expect for your design.

  • Ask for a full verification test environment. A full verification environment provides a set of models for different stimuli to verify the IP functionality and makes the overall chip verification less complicated.

  • IPs should be accompanied by detailed documentation, such as datasheet, databook, user's guide, application notes, etc. Proper documentation offers valuable information on timing, interface definition, and different configurations for specific applications.

  • Allocate a certain period of time to become familiar with the interfaces and functionality of the outsourced IP. It is quite common that IP interfaces do not match the rest of the system interface causing additional work to be done in the integration process. This could change the project schedule if the additional integration time is not included in the project timeline.

  • Make an agreement with the IP provider for technical support during the integration process. There are many instances when an IP has to be customized for a specific design at the integration time and only the IP provider is able to perform these modifications. Therefore, it is necessary to have the IP provider's support through the integration process.

We will cover more on IP verification and integration in Chapter 3. Table 1.3 shows several examples of Silicon IPs.

Table 1.3. Examples of IPs

Category

Intellectual Property

Processor

ARM7, ARM9, and ARM10, ARC

Application-Specific DSP

ADPCM, CELP, MPEG-2, MPEG-4, Turbo Code, Viterbi, Reed Solomon, AES

Mixed Signal

ADCs, DACs, Audio Codecs, PLLs, OpAmps, Analog MUX

I/Os

PCI, USB, 1394, 1284, E-IDE, IRDA

Miscellaneous

UARTs, DRAM Controller, Timers, Interrupt Controller, DMA Controller, SDRAM Controller, Flash Controller, Ethernet 10/100 MAC


   
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From ASICs to SOCs. A Practical Approach
From ASICs to SOCs: A Practical Approach
ISBN: 0130338575
EAN: 2147483647
Year: 2003
Pages: 61

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