5.4. PCI-X

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PCI-X is a compatible extension of the existing PCI bus, jointly developed by Compaq, HP, and IBM. It is fully backward compatible with the PCI 2.1 protocol. PCI-X enables the design of systems that can operate at frequencies up to 133MHz using a 64-bit bus width, providing burst transfer rates higher than 1GB/s.

Figure 5-8 shows an illustration of the PCI-X architecture.

Figure 5-8. PCI-X architecture.


The PCI-X specification is an open industry standard available from the PCI Special Interest Group as an addendum to the PCI Local Bus 2.2 specification.

PCI-X enhancements to the PCI bus include the following:

  • Backward compatibility Because PCI-X is backward compatible with PCI, existing PCI cards work in a PCI-X environment. In fact, you can use both PCI-X and PCI cards on the same bus. However, the PCI-X bus defaults to the speed of the slowest card on the bus.

  • Forward compatibility PCI-X cards can be designed as universal cards, which means they can plug into either 3.3V I/O slots (66MHz and faster) or 5V I/O slots (33MHz). However, the added functionality and speed of a PCI-X card is not fully realized if it is used on an existing PCI bus.

  • Speed PCI-X is a 64-bit bus that runs at speeds up to 133MHz. Several other design improvements increase bus efficiency, leading to even more I/O throughput. Compared to the performance of a typical 32-bit/ 33MHz PCI implementation, PCI-X delivers up to a 10x improvement in performance.

  • Number of slots Because of stringent electrical requirements, PCI systems at 66MHz can support only one or two slots. PCI-X solves this limitation because it can support four or more slots at 66MHz.

The 64-bit PCI-X architecture runs at speeds up to 133MHz, providing burst transfer rates greater than 1GB/s. This critical I/O bandwidth is needed for industry-standard servers running enterprise applications such as Gigabit Ethernet, Fibre Channel, Ultra3 SCSI, and cluster interconnects.

In addition to performance improvements, PCI-X also increases the fault isolation of the PCI bus by helping the operating system work more effectively with adapters to better manage error conditions.

PCI-X offers both added performance and flexibility, minimizing the trade-off between PCI slots and bus speed.

Example

Based on preliminary simulation testing, a 66MHz four-slot implementation of PCI-X shows more than a 25% increase in I/O performance over a conventional PCI bus running at its maximum configuration (64 bits/ 66MHz). It is also possible to use multiple PCI-X buses at different speeds, providing a combination of ultra-high performance and maximum slot capacity.


As an open specification, PCI has been the foundation of continuous innovation throughout the industry. But the evolution of computing is driving I/O bandwidth requirements beyond the capacity of PCI 2.2, PCI-X, or any multidrop parallel bus architecture.

5.4.1 PCI-X Performance

Based on preliminary simulation testing, a 66MHz PCI-X implementation shows an increase of more than 30% in I/O performance over a conventional PCI bus running at its maximum configuration of 64 bits, 66MHz. This performance improvement is shown in Figure 5-9.

Figure 5-9. PCI-X performance compared to conventional PCI.


Using a 4KB block size typical of Gigabit Ethernet or Ultra3 SCSI controllers, the PCI-X protocol improved performance by up to 34% over the conventional PCI protocol. This improvement assumes an ideal memory controller with a 32-byte processor cache line and ideal 64-bit PCI adapters.

PCI-X achieves higher performance as a result of two primary differences between conventional PCI and PCI-X. First, PXI-X features higher clock frequencies made possible by a register-to-register protocol rather than an immediate protocol. Second, PCI-X includes new protocol enhancements such as attribute phase, split transactions, optimized wait states, and standard block-size movements

Note

More information about PCI-X performance is available at the PCI Special Interest Group Web site at http://www.pcisig.com.


5.4.2 PCI-X Hierarchical Structure

It is possible to use multiple PCI-X buses operating at different speeds to increase performance and gain more slots. Figure 5-10 illustrates how this can be accomplished.

Figure 5-10. PCI-X bridges allow PCI to link up to 256 bus segments.


A PCI-X bus running at 133MHz can support multiple slots at different speeds through PCI-X to PCI-X bridges as shown in this diagram.

PCI-X supports up to 256 bus segments. Each segment is initialized separately so that different operating frequencies can be used.

5.4.3 PCI-X System Flexibility

In addition to increased performance, PCI-X offers flexibility of system design. For solutions that require maximum connectivity, PCI-X can support four expansion slots operating at 66MHz. For maximum speed, PCI-X can support a single slot at 133MHz.

The following table shows performance and slot comparison between PCI and PCI-X.

Bus Width

Bus Frequency

Bus Bandwidth

PCI Slots

PCI-X Slots

32 bits

33MHz

133MB/s

N/A

64 bits

33MHz

267MB/s

64 bits

66MHz

533MB/s

64 bits

100MHz

800MB/s

N/A

64 bits

133MHz

1067MB/s

N/A


Note

PCI-X is fully backward compatible with conventional PCI systems. PCI-X requires no device driver or operating system modification for existing hardware. Changes to the device drivers are required only to take advantage of the new features such as transaction byte count.


5.4.4 PCI Compared to PCI-X

The PCI-X register-to-register protocol provides better performance than the PCI protocol through the use of technological advances, such as the following:

  • Timing enhancements

  • Attribute phase

  • Split transaction report

  • Optimized wait states

  • Standard block-size movements

5.4.4.1 PCI PROTOCOL

With conventional PCI, the time available to decode a transaction decreases as the bus frequency increases from 33MHz to 66MHz.

The conventional PCI bus uses an immediate protocol. With a conventional PCI device, the following steps occur when the device switches a control signal, as illustrated in Figure 5-11:

1. On the rising clock edge, the device switches the signal to a high or low state on the PCI bus.

2. The signal propagates across the bus (propagation delay).

3. During the same clock cycle, the receiving device decodes the signal to determine whether the signal is for the receiving device and whether it must respond by switching one of its outputs.

4. The receiving device responds immediately, that is, in the next clock cycle.

Figure 5-11. How a PCI device switches a control signal.


With a 33MHz clock frequency, the time allocated for the decode logic is 7ns of the total 30ns clock cycle time. At 33MHz, this is sufficient time for the receiving device to respond on the next rising clock edge. However, when the bus frequency is doubled to 66MHz (with a clock cycle time of 15ns), the time available to perform this logic is reduced to 3ns.

These time constraints of the conventional PCI specification make it difficult to design a conventional PCI bus or adapter for 66MHz.

5.4.4.2 PCI-X REGISTER-TO-REGISTER PROTOCOL

In comparison to PCI, the PCI-X register-to-register protocol functions as shown in Figure 5-12.

Figure 5-12. The PCI-X protocol allows an entire clock cycle for the decode logic to occur.


With the PCI-X register-to-register protocol, the following steps occur:

1. On the rising clock edge, the device switches the signal to a high or low state on the PCI-X bus.

2. The signal propagates across the bus.

3. The signal is sent to a register, or flip-flop, that holds the signal state until the next clock cycle.

4. The receiving device has a full clock cycle to decode the signal and determine the appropriate response.

5. The receiving device responds two full clock cycles after the sending device first switched the signal.

PCI-X eases the timing constraints by allowing an entire clock cycle for the decode logic to occur. The net difference is that PCI-X transactions generally require one clock cycle more than conventional PCI transactions. A write transaction that completes in nine clock cycles for conventional PCI will complete in ten clock cycles for PCI-X.

5.4.4.3 TIMING DIFFERENCES

Figure 5-13 illustrates the actual time difference between the PCI and PCI-X protocols for a typical write transaction.

Figure 5-13. Time differences between PCI and PCI-X for a write transaction.


With the timing constraints reduced, it is much easier to design adapters and systems to operate at 66MHz and greater. System designers can benefit from the eased timing constraints by choosing maximum performance with a single PCI-X slot at 133MHz or maximum connectivity with additional slots on the PCI-X bus.

If a system designer chooses to increase the bus frequency, the actual time required to complete the transaction is greatly reduced, even though a clock cycle has been added. A transaction that takes 9 cycles at 33MHz will finish in 270ns. A PCI-X transaction that takes 10 cycles at 133MHz will finish in 75ns, which is a 72% reduction in transaction time.

If a system designer chooses to keep the frequency at 66MHz, slots can be added to the bus segment. Because more time is budgeted for a signal to propagate from one device to another, the signal can traverse a longer path across multiple slots.

5.4.4.4 ATTRIBUTE PHASE

The PCI-X protocol includes a new transaction phase called the attribute phase that uses a 36-bit attribute field that describes bus transactions in more detail than the conventional PCI specification allows. It follows immediately after the address phase and contains several bit assignments that include information about the following:

  • The size of the transaction

  • Ordering of transactions

  • Cache snooping requirements

  • Identity of the transaction initiator

The following enhancements are included within the attribute phase:

  • Relaxed ordering

  • Non-cache-coherent transactions

  • Transaction byte count

  • Sequence number

5.4.4.5 SPLIT TRANSACTION SUPPORT

The conventional PCI protocol supports delayed transactions. With a delayed transaction, the device requesting data must poll the target to determine when the request has been completed and its data is available.

With a split transaction as supported in PCI-X, the device requesting the data sends a signal to the target. The target device informs the requester that it has accepted the request. The requester is free to process other information until the target device initiates a new transaction and sends the data to the requester. Thus, split transactions enable more efficient use of the bus.

5.4.4.6 OPTIMIZED WAIT STATES

Conventional PCI devices often add extra clock cycles, or wait states, to their transactions. The wait states are added to stall the bus if the PCI device is not ready to proceed with the transaction, which can slow bus throughput dramatically.

PCI-X eliminates the use of wait states, except for initial target latency. When a PCI-X device does not have data to transfer, it removes itself from the bus so that another device can use the bus bandwidth. This removal provides more efficient use of bus and memory resources.

5.4.4.7 STANDARD BLOCK-SIZE MOVEMENTS

With PCI-X, adapters and bridges (host-to-PCI-X and PCI-X-to-PCI-X) are permitted to disconnect transactions only on naturally aligned 128-byte boundaries. This encourages longer bursts and enables more efficient use of cache line-based resources such as the processor bus and main memory. It also facilitates a more pipelined architecture within PCI-X devices.

5.4.5 Adapter Card Selection

PCI-X cards perform in current PCI systems just like conventional 66MHz cards, as illustrated in Figure 5-14.

Figure 5-14. How PCI-X cards can be used in current PCI systems.


5.4.5.1 CARD SLOT SUPPORT

Many PCI cards and PCI slots operate at a single voltage only, either 5V or 3.3V. PCI slots and cards are keyed so that a 5V card cannot be inserted into a dedicated 3.3V slot and a 3.3V card cannot be inserted into a dedicated 5V slot.

Universal PCI cards are universally keyed. They can operate at either voltage and fit into either a 5V slot or a 3.3V slot.

PCI voltages have changed with each newer specification:

  • All PCI slots use 5V for power, therefore the voltage listed for a card refers to the voltage used for its signaling lines.

  • PCI 2.1 specification uses 5V signal lines with 3.3V signal line support optional. A PCI 2.1-compliant system board (chipset) might not have physical 3.3V signal lines because of the optional support and are keyed to only accept cards that support 5V signal lines.

  • PCI 2.2 specification required using 3.3V signal lines. 3.3V signal lines are required on all 66MHz, 100MHz, or 133MHz PCI slots.

  • PCI-X slots use only 3.3V signal lines.

You can use 32-bit/33MHz PCI cards in PCI-X slots if they are universal voltage that is, if they work with both 5V and 3.3V voltages. PCI card and slot keys are meant to match signaling voltages. The 5V-only PCI cards are keyed so that they cannot be installed in a PCI-X slot. Some PCI-X cards work only with 3.3V voltage, so they are keyed so that they cannot be installed in a 5V slot.

Note

If a 32-bit/33MHz 3.3V card is installed on the PCI-X bus, it automatically forces all the cards in the same PCI-X bridge to work at 32-bit/33MHz speed.


5.4.5.2 INTEROPERABILITY MATRIX

Figure 5-15 illustrates how PCI and PCI-X cards function in a conventional system or a PCI-X system.

Figure 5-15. PCI and PCI-X interoperability matrix.


A PCI-X device can run at speeds from 33 to 133MHz. In a PCI-X system, the system runs at the speed of the slowest device. Because of backward-compatibility requirements, all PCI-X devices must be able to run at lower speeds to work in older systems or in PCI-X systems with a slower device or PCI device.

The PCI-X bus can accommodate only one PCI-X device at 133MHz, two devices at 100MHz, and four or more devices at 66MHz.

5.4.6 PCI Hot Plug Support in PCI-X

PCI-X technology supports PCI Hot Plug and offers a great deal of latitude in the design of hot-pluggable controllers. Certain considerations affecting hardware and software must be taken into account when migrating to PCI-X.

The hot-pluggable controller must

  • Provide the hot-pluggable system driver with the means to check the PCIXCAP pin to identify PCI-X adapters.

  • Drive the PCI-X initialization pattern on the bus with the proper timing before the rising edge of RST# for that slot.

  • Coordinate with the arbitrator for bus ownership during hot insertion.

The hot-pluggable system driver must read the M66EN and PCIXCAP pin on the inserted card to ensure that the inserted adapter supports the bus frequency and operating mode of the bus.

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    HP ProLiant Servers AIS. Official Study Guide and Desk Reference
    HP ProLiant Servers AIS: Official Study Guide and Desk Reference
    ISBN: 0131467174
    EAN: 2147483647
    Year: 2004
    Pages: 278

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