The Timed Structures

Doesn't it seem like every While Loop has some kind of timing function inside of it? Wouldn't it be great if the timer were somehow built into the While Loop? Well, if you take a look at the Programming>>Structures>>Timed Structures palette (shown in Figure 6.59), you'll find a set of tools that make While Loop (as well as Sequence Structure) timing and synchronization possible.

Figure 6.59. Timed Structures palette

Timed Structures are only available on Windows. They were designed especially for use in time-critical LabVIEW RT and FPGA applications, and those LabVIEW modules are not supported on Mac OS X and Linux.

Timed Structures and VIs allow you control the rate and priority at which a timed structure executes its subdiagram, synchronize the start time of timed structures, create timing sources, and establish a hierarchy of timing sources.

The Timed Loop and the Timed Sequence (which you'll learn about next) have several nodes attached to their frames. These are used for configuring the loops and obtaining information about their execution.

Probably the biggest conceptual hurdle in using the timed structures is that each timed structure may be named (using a string). The name string is passed into the Name terminal on the outer-left node of the Timed Structure. This name is then used as a reference to the timed structure when operating on it using the time structure VIs, which you will also learn about shortly. Similarly, timing sources and synchronization groups are also named (using a string) and referenced by their names.

OK, now you're ready for the nitty gritty details of the timed structures and VIs.

The Timed Loop

The Timed Loop (shown in Figure 6.60) executes one or more subdiagrams, or frames, sequentially each iteration of the loop at the period you specify. Use the Timed Loop when you want to develop VIs with multi-rate timing capabilities, precise timing, feedback on loop execution, timing characteristics that change dynamically, or several levels of execution priority. Right-click the structure border to add, delete, insert, and merge frames. If you use the Timed Loop in an FPGA VI, the loop executes one subdiagram at the same period as an FPGA clock.

Figure 6.60. The Timed Loop structure

The Timed Sequence

The Timed Sequence (shown in Figure 6.61) consists of one or more task subdiagrams, or frames, that execute sequentially. Use the Timed Sequence when you want to develop VIs with multi-rate timing capabilities, precise timing, execution feedback, timing characteristics that change dynamically, or several levels of execution priority. Right-click the structure border to add, delete, insert, and merge frames.

Figure 6.61. The Timed Sequence structure

The Timed Structure VIs

The following VIs are used to control timed structures and their timing sources (see Figures 6.626.66).

Figure 6.62. Build Timing Source Hierarchy

Figure 6.63. Clear Timing Source

Figure 6.64. Create Timing Source

Figure 6.65. Stop Timed Structure

Figure 6.66. Synchronize Timed Structure Starts

Creates a hierarchy of timing sources based on the names you enter in timing source names. The hierarchy determines the order in which the timing sources start. The parent timing source does not start until after the timing sources in hierarchy name start. Use this VI when you have timing sources that have signal dependencies, such as DAQ counters routed to drive analog input connections. In such a case, the counter timing source acts as the parent.

Stops and deletes the timing source you created or specified for use by another resource. If the timing source is associated with a DAQmx task, the VI also clears the task. The VI cannot reuse a name until all Timed Loops attached to the timing source terminate.

Creates a timing source you use as the timing source in the Timed Loop. Each timing source has its own unit of timing and/or start time and does not start until the first Timed Loop that uses the timing source starts. You must manually select the polymorphic instance you want to use. (You can choose from either a 1kHz timing source or a 1 MHz timing source.)

Stops the Timed Loop or Timed Sequence you enter in name. If you attempt to abort a running Timed Loop, the Timed Loop executes another iteration and returns Aborted in the Wakeup Reason output of the Left Data node.

Synchronizes the start of Timed Loops or Timed Sequences you enter in timed structure names by adding the names to the synchronization group you specify in synchronization group name. All timed structures in a synchronization group wait until all the structures are ready to execute.