Practical FPGA Programming in C - page 1
- Practical FPGA Programming in C
- Practical FPGA Programming in C
- Table of Contents
- Copyright
- Prentice Hall Modern Semiconductor Design Series
- Foreword
- Why is this book of interest to the hardware folks?
- And what about the software guys and gals?
- So what s the catch?
- Preface
- C Language for FPGA-Based Hardware Design?
- Compelling Platforms for Software Acceleration
- The Power to Experiment
- How This Book Is Organized
- Where This Book Came From
- Acknowledgments
- Chapter1.The FPGA as a Computing Platform
- Section 1.1. A Quick Introduction to FPGAs
- Section 1.2. FPGA-Based Programmable Hardware Platforms
- Section 1.3. Increasing Performance While Lowering Costs
- Section 1.4. The Role of Tools
- Section 1.5. The FPGA as an Embedded Software Platform
- Section 1.6. The Importance of a Programming Abstraction
- Section 1.7. When Is C Language Appropriate for FPGA Design?
- Section 1.8. How to Use This Book
- Chapter2.A Brief History of Programmable Platforms
- Section 2.1. The Origins of Programmable Logic
- Section 2.2. Reprogrammability, HDLs, and the Rise of the FPGA
- Section 2.3. Systems on a Programmable Chip
- Section 2.4. FPGAs for Parallel Computing
- Section 2.5. Summary
- Chapter3.A Programming Model for FPGA-Based Applications
- Section 3.1. Parallel Processing Models
- Section 3.2. FPGAs as Parallel Computing Machines
- Section 3.3. Programming for Parallelism
- Section 3.4. Communicating Process Programming Models
- Section 3.5. The Impulse C Programming Model
- Section 3.6. Summary
- Chapter4.An Introduction to Impulse C
- Section 4.1. The Motivation Behind Impulse C
- Section 4.2. The Impulse C Programming Model
- Section 4.3. A Minimal Impulse C Program
- Section 4.4. Processes Streams Signals, and Memory
- Section 4.5. Impulse C Signed and Unsigned Datatypes
- Section 4.6. Understanding Processes
- Section 4.7. Understanding Streams
- Section 4.8. Using Output Streams
- Section 4.9. Using Input Streams
- Section 4.10. Avoiding Stream Deadlocks
- Section 4.11. Creading and Using Signals
- Section 4.12. Understanting Registers
- Section 4.13. Using Shared Memories
- Section 4.14. Memory and Stream Performance Considerations
- Section 4.15. Summary
- Chapter5.Describing a FIR Filter
- Section 5.1. Design Overview
- Section 5.2. The FIR Filter Hardware Process
- Section 5.3. The Software Test Bench
- Section 5.4. Desktop Simulation
- Section 5.5. Application Monitoring
- Section 5.6. Summary
- Chapter6.Generating FPGA Hardware
- Section 6.1. The Hardware Generation Flow
- Section 6.2. Understanding the Generated Structure
- Section 6.3. Stream and Signal Interfaces
- Section 6.4. Using HDL Simulation to Understand Stream Protocols
- Section 6.5. Debugging the Generated Hardware
- Section 6.6. Hardware Generation Notes
- Section 6.7. Making Efficient Use of the Optimizers
- Section 6.8. Language Constraints for Hardware Processes
- Section 6.9. Summary
- Chapter7.Increasing Statement-Level Parallelism
- Section 7.1. A Model of FPGA Computation
- Section 7.2. C Language Semantics and Parallelism
- Section 7.3. Exploiting Instruction-Level Parallelism
- Section 7.4. Limiting Instruction Stages
- Section 7.5. Unrolling Loops
- Section 7.6. Pipelining Explained
- Section 7.7. Summary
- Chapter8.Porting a Legacy Application to Impulse C
