Section 2.2. Reprogrammability, HDLs, and the Rise of the FPGA

2.2. Reprogrammability, HDLs, and the Rise of the FPGA

Three factors combined in the mid- to late 1980s to cause a dramatic change in how programmable logic was applied, and in its applicability to hardware acceleration of software computations. These factors were reprogrammability, more flexible interconnect architectures, and tools for the automated synthesis of circuitry from standard hardware description languages.

Reprogrammabilitythe ability of a device to be erased and/or overwritten with new programming datawas a critical advancement over first-generation programmable logic devices, which, once programmed, were in effect fixed-function custom hardware devices. Reprogrammability had enormous implications for hardware designers creating complex systems. Not only could these systems be quickly developed and tested as prototypes (with no need to throw away experimental versions of a given hardware function), but field upgrades of hardware algorithms were now possible, just as it had become possible to provide field upgrades of software and PROM-based firmware.

The new, more flexible device architectures represented by FPGA devices (which were produced by Xilinx, Inc., Altera Corporation, and others) were also critical. These devices had dramatically higher logic capacities and more general-purpose features than had existed previously, and therefore provided a new set of opportunities for performing complex computations directly in hardware.

Finally, the emergence of more powerful logic synthesis software tools and the development and eventual standardization of two powerful hardware description languages, VHDL and Verilog, made it possible for application developers to work at a higher level of abstraction, leaving to the design tools the details of actual implementation of an algorithm as low-level logic gates, registers, and the like. A sample VHDL source file describing a cyclic redundancy check (CRC) module is shown in Figure 2-3. VHDL and Verilog descriptions can be relatively abstract (they "feel" like programming languages), but if the described function is intended for actual compilation to hardware, through the use of a logic synthesis tool, it must be assumed that the programmer has a somewhat detailed knowledge of the underlying hardware and, in particular, how clocked logic is implemented in low-level registers. In fact, this is a key characteristic of programming for FPGAs using VHDL or Verilog: the designer must understand the clock boundaries and must write logic descriptions that clearly define an application's clocked (or timed) behavior.

By the start of the 1990s, it was clear that programmable logic devices had matured to the point where high-performance software algorithms and even complete applications could be implemented directly in hardware. Throughout the 1990s, researchers involved in the domain of reconfigurable FPGA-based computing published results that were often surprising, demonstrating the huge potential for algorithm acceleration using these devices, which were growing in capacity and power in lockstep with Moore's Law, which states that the number of transistors (or the data density in more recent definitions) in integrated circuits will double every 18 months. Traditional CISC and RISC processors, on the other hand, continue to suffer from lower silicon efficiencies when measured as a percentage of transistors actually capable of doing useful work at any given time.

Figure 2-3. VHDL design file describing a CRC generator.

 ----------------------------- -- 8-bit serial CRC generator -- library ieee; use ieee.std_logic_1164.all; entity crc8s is   port (Clk, Rst, Din: in std_ulogic;         CRC: out std_ulogic_vector(15 downto 0)); end crc8s; architecture behavior of crc8s is   signal X: std_ulogic_vector(15 downto 0); begin   process(Clk,Rst)   begin     if Rst = '1' then        X <= (others=> '1');     elsif rising_edge(Clk) then        X(0)  <= Din xor X(15);        X(1)  <= X(0);        X(2)  <= X(1);        X(3)  <= X(2);        X(4)  <= X(3);        X(5)  <= X(4) xor Din xor X(15);        X(6)  <= X(5);        X(7)  <= X(6);        X(8)  <= X(7);        X(9)  <= X(8);        X(10) <= X(9);        X(11) <= X(10);        X(12) <= X(11) xor Din xor X(15);        X(13) <= X(12);        X(14) <= X(13);        X(15) <= X(14);     end if;   end process;   CRC <= X; end behavior;  

And yet, at the turn of the century, the primary use of FPGAs was still almost overwhelmingly for traditional hardware functions: controllers, interface logic, and peripheral integration. FPGA-based computing had not yet caught hold.

In recent years, two important developments have combined with ever-increasing device densities to make FPGA-based computing practical for mainstream applications. The first of these developments is the availability of full-featured embedded FPGA processor cores, including the MicroBlaze and PowerPC cores available from Xilinx, the Nios and Nios II processor cores available from Altera, and other processor cores available from third-party IP suppliers. The second development, and the primary subject of this book, is the availability of software-to-hardware compiler tools.