Section 2.1. The Origins of Programmable Logic

2.1. The Origins of Programmable Logic

Most industry watchers point to the introduction in 1975 of the field programmable logic array (the precursor of today's FPGA) as the birth of programmable logic, but the history of programmable logic actually goes back some years earlier. The programmable devices we know today are direct ancestors of experimental devices produced in the late 1960s and early 1970s by Harris Semiconductor (then known as Radiation, Inc.) and General Electric.

The first of these devices were primitive diode matrices that were used as controllers for such diverse applications as television channel selectors, HAM radio tuners, and pipe organ switching systems, as well as in emerging defense and space applications. These relatively crude devices were soon replaced by more capable logic devices based on arrays of combinatorial gates, typically AND and OR gates arranged to form a sum-of-products or product-of-sums architecture.

The key development that made programmable logic a practical alternative for general-purpose logic design (and for use in performing special-purpose computations) was the ability to program the devices after manufacturing using low-cost equipment. The basic technology involved creating a mask layer of fusible links that were selectively removedliterally melted awayusing high voltages applied to device pins by specialized programming equipment. This reliable and low-cost programming method, which was initially developed to create one-time-programmable read-only memories (or ROMs) is still used today for many simpler programmable logic devices.

The first field-programmable logic array (FPLA) devices were released in 1975 by competitors Intersil Corporation and Signetics Corporation. These first FPLAs were quite powerful for their time and provided enough capacity and I/O resources to implement a wide variety of functions including state machines, decoding logic, and basic arithmetic operations. When collected into larger multi-chip programmed systems, these devices were capable of creating high-performance computational devices including minicomputers such as the DEC VAX 11/750 and Data General Eclipse.

New Methods of Design Are Required

The Signetics 82S100 FPLA device was the first programmable logic device to achieve a modest level of commercial success. Its history provides a useful analogy for today's newly emerging programmable platforms and the shift in design methods required when moving to radically different types of logic and/or computing platforms.

When it was first introduced, the 82S100 was a thing quite alien to most embedded systems designers, and to digital logic designers as well; was it a logic device or some kind of controller? Using off-the-shelf TTL devices (which represented basic logic functions such as ANDs, ORs, exclusive ORs, and set/reset flip-flops) had become a standard method of digital design in 1975, and these new devices did not fit into the schematic-oriented, building-block design methods of the time. Even with a relatively high level of documentation and applications support, most digital designers rejected the new devices as being too difficult to use. This difficulty stemmed from the conceptual differences between how designers had expressed their applications in the past and how they were forced to express them when using programmable logic devices.

Applications that were to be implemented using FPLAs had to be described in an unfamiliar tabular format that bore little resemblance to the block diagrams and Boolean equations that had previously been used to work out a logic problem. The data from this tabular form was subsequently entered into a hardware device programmer into which the chip was inserted for programming. This was quite different from the TTL design process, in which components were selected from a data book and arranged to create larger systems of interconnected logic.

Early HDLs Increase Design Abstraction

Programmable logic devices didn't gain widespread acceptance until the late 1970s, when Monolithic Memories, Inc., introduced its Programmable Array Logic (PAL) series of devices. These devices, which were designed by John Birkner and H. T. Chua, had a number of advantages over the earlier FPLA devices, including more standard packaging, higher speeds, and more emphasis on compatibility with existing and widely popular TTL devices.

One important factor in the success of the PAL was a design language called PALASM (PAL Assembler), which was a compiler program that converted applications described using familiar Boolean equations into the necessary programming data. PALASM, in fact, was one of the first hardware description languages (HDLs) and remains in use today by many thousands of engineers and students. A sample PALASM source file is shown in Figure 2-1. As shown in this example, PALASM provides more than just a logic description. It also provides, in the function table section, a set of tests to be applied to the device after programming. This was an important language feature because device programming was not always successful. The devices could have faulty programmable fuse elements, the programming equipment could be out of spec, or the logic equations themselves could be incorrect. Providing hardware test data in the form of test vectors right in the design itself eliminated the vast majority of later in-system problems.

Figure 2-1. PALASM design file representing a 4-bit counter with synchronous clear.

 PAL16R4 PAL COUNT4 4-bit counter with synchronous clear Clk  Clr   NC  NC  NC  NC  NC  NC  NC  GND OE   NC    NC /Q3 /Q2 /Q1  /Q0 NC  NC  VCC  Q3 :=  Clr     + /Q3 * /Q2 * /Q1 * /Q0     +  Q3 *  Q0     +  Q3 *  Q1     +  Q3 *  Q2  Q2 :=  Clr     + /Q2 * /Q1 * /Q0     +  Q2 *  Q0     +  Q2 *  Q1  Q1 :=  Clr     + /Q1 * /Q0     +  Q1 *  Q0  Q0 :=  Clr     + /Q0 FUNCTION TABLE OE CLR Clk   /Q0 /Q1 /Q2 /Q3 ---------------------------- LH     C      L  L  L  L LL     C      H  L  L  L LL     C      L  H  L  L LL     C      H  H  L  L LL     C      L  L  H  L LH     C      L  L  L  L ---------------------------- 

Regardless of its original rationale, this simple idea of using the same language to describe both the application and the test conditions for that application has been a key aspect of all subsequent hardware description languages. As devices became more complex and the capabilities of programmable logic design languages and tools increased, these test vectors (and other higher-level abstractions for testing) were used not only to test the programmed devices, but to provide input to software-based device simulations as well.

Larger Devices, More-Complex Programming Tools

By the early 1980s, many companies were providing programmable logic devices, each with its own unique set of architectural features. As these devices became more complex and varied, the need grew for higher levels of design abstraction and for automated conversion of higher-design descriptions to programmable logic implementations. Simulation tools also became increasingly important; the size and complexity of programmable logic applications were now growing to the point where testing based on device inputs and outputs (by providing simple device test vectors) was not sufficient.

In response to these challenges, in March of 1983 a company called Assisted Technology released its CUPL (Common Universal tool for Programmable Logic) compiler. Shortly thereafter, Data I/O Corporation (the largest manufacturer of device programming hardware at the time) released its ABEL (Advanced Boolean Expression Language) product. Both of these software products, and the design languages they encapsulated, were evolutionary advances over the earlier PALASM and PALASM-like tools. They represented the first commercially successful attempts at creating relatively target-independent methods of programming hardware from a higher (software-like) level of abstraction.

Both ABEL and CUPL allowed logic designs to be described in formats ranging from higher-level logic equations (which included such things as relational and math operators) to large state diagrams describing complex control logic (as shown in Figure 2-2). Using such tools, it was now feasible for an embedded systems designer who had little or no knowledge of circuit design fundamentals and only the most rudimentary understanding of digital logic to describe and compile a high-performance algorithm directly into hardware.

Although the use of programmable logic devices for creating logic circuits grew dramatically in the early to mid-1980s, they did not take hold among embedded systems designers and programmers due to their relatively small size and the wide availability and low cost of standard microcontrollers. While microcontrollers were (and remain) exceptionally slow in terms of data throughput relative to what is possible using programmable logic, the tremendous flexibility provided by microcontrollers and microprocessors, along with their ability to host much larger algorithms and applications, made them the obvious choice for all but the simplest and most performance-critical functions.

Figure 2-2. ABEL design file using state diagram syntax to describe a simple sequence detector (test vectors are removed for brevity).

 module SequenceDetect title '8-bit 10111101 sequence detector example'  declarations  DIN, CLK, ARST pin;          " Inputs SEQ pin istype 'reg';        " Registered output Q2,Q1,Q0 pin istype 'reg';   " State registers " Define the state values using optimal encoding SREG = [Q2,Q1,Q0];     S0 = [ 0, 0, 0];    S1 = [ 0, 0, 1];    S2 = [ 0, 1, 1];    S3 = [ 1, 1, 1];    S4 = [ 1, 0, 1];    S5 = [ 1, 1, 0];    S6 = [ 0, 1, 0];    S7 = [ 1, 0, 0]; equations "Define the async reset and clock signals [Q2,Q1,Q0].AR = ARST; [Q2,Q1,Q0].CLK = CLK; "Define the state transitions state_diagram SREG STATE S0:   IF DIN == 1 THEN S1 ELSE S0; STATE S1:   IF DIN == 0 THEN S2 ELSE S0; STATE S2:   IF DIN == 1 THEN S3 ELSE S0; STATE S3:   IF DIN == 1 THEN S4 ELSE S0; STATE S4:   IF DIN == 1 THEN S5 ELSE S0; STATE S5:   IF DIN == 1 THEN S6 ELSE S0; STATE S6:   IF DIN == 0 THEN S7 ELSE S0; STATE S7:   IF DIN == 1 THEN S0 WITH Z:=1; ELSE S0; end SequenceDetect