Index[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Z] PACT PAL Assembler PALASM parallel computing processes programming parallelism coarse-grained extreme levels of programming for 2nd spatial statement-level 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th system-level 2nd 3rd partitioning system-level 2nd PCI Pentium peripheral integration 2nd Photoshop PIC processor 2nd picoChip pipeline generation 2nd 3rd goal 2nd 3rd 4th hardware size loop performance 2nd rate 2nd system-level 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th PIPELINE pragma pipelining 2nd 3rd 4th 5th pixel stream place-and-route 2nd platform FPGA-based 2nd selection 2nd Platform Studio 2nd Platform Support Package 2nd PLB Posix potassium channels PowerPC 2nd 3rd 4th 5th 6th pragma PIPELINE 2nd 3rd 4th StageDelay UNROLL 2nd 3rd 4th process 2nd 3rd 4th 5th 6th 7th run function synchronization of 2nd 3rd understanding 2nd 3rd 4th 5th processing elements (PEs) machine model processor as test generator benchmarks considerations core 2nd embedded 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th hard core MicroBlaze 2nd 3rd 4th performance peripherals 2nd soft 2nd Processor Local Bus [See PLB] producer process 2nd 3rd 4th programmable array logic [See PAL] hardware platform 2nd logic 2nd origins of 2nd 3rd 4th 5th 6th programming abstraction 2nd 3rd 4th 5th model 2nd 3rd communicating processes Impulse C 2nd 3rd streams-oriented prototyping 2nd of hardware rapid |