S

Index

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Z]

SDRAM
secondary clock
SERDES
     for data streaming 2nd 3rd
     handshaking
     initializing
     synchronization pattern
     transceiver
serial interface 2nd
serializer/deserializer [See SERDES]
shared memory 2nd
     performance considerations 2nd 3rd 4th 5th 6th
     using 2nd 3rd
shift operand
signal
     creating 2nd
     interface
     overview of 2nd
     posting
     value
     wait mode
     waiting for
signed type
Signetics Corporation
Silicon Graphics
SIMD
simulation
     consumer process
     cycle-accurate
     DES encryption 2nd
     desktop
     hardware
     library
     producer process
     software 2nd
     source-level debugging
     test bench
     tools
     VHDL
simulator
     hardware
SISD
Snider, Dr. Ross
soft processor 2nd
software
     process
     simulation 2nd
     test bench
software-based methods
solution space
SOPC Builder 2nd
SP box 2nd
Spartan- 2nd
spatial parallelism
SRAM
stage
Stage Master
StageDelay pragma 2nd
standard processor
state machine
     generated from C
     SERDES interface
stdio.h
stream 2nd 3rd 4th
     closing
     custom interface 2nd 3rd 4th 5th 6th 7th 8th
     datatype
     deadlocks
     for input
     for output
     hardware
     I/O 2nd 3rd 4th
     interface 2nd 3rd
     macro interfaces 2nd
    mode
         read
         write
     nonblocking
     opening
     overview of 2nd 3rd 4th
     parameters
     performance 2nd
         considerations 2nd 3rd 4th 5th 6th
     protocol
     read mode
     reading
     write mode
Streams-C
struct
structured ASIC
SUIF
supercomputing
synchronization
     pattern
     process 2nd 3rd
synthesis
system
     architect
     integration 2nd
     on a programmable chip 2nd 3rd 4th 5th
system-level pipeline 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th
SystemC 2nd