In this introductory chapter, we defined an SOC and some of its differences from a traditional ASIC. A key concept in SOC design is the usage of different IPs. This by itself creates a big challenge in SOC design, namely IP integration.
Reuse methodology is an important factor in SOC designs that reduces time-to-market (TTM). We cover more on ASICs and SOCs, including verification techniques, in Chapters 2 and 3, respectively.
Chapter 4 deals with the physical design domain that is common to both ASICs and SOCs. Once you have a netlist for the proposed IC (ASIC or SOC), then you enter the world of the physical domain.
Chapter 5 covers low-power design concepts and techniques that again are common to both ASICs and SOCs. Several methods of power optimization at different levels of abstraction will be covered. These techniques include algorithm, architecture, Register Transfer, and gate-level optimizations.