1.7 References

   

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1. M. Keating and P. Bricaud. Reuse Methodology Manual for System-on-a-Chip Designs . Norwell, MA: Kluwer Academic Publishers, 1998.

2. F. Nekoogar. Timing Verification of Application-Specific Integrated Circuits (ASICs) . Upper Saddle River, NJ: Prentice Hall PTR, 1999.

3. P. Rashinkar, P. Paterson, and L. Singh. System-on-a-Chip Verification Methodology and Techniques . Norwell, MA: Kluwer Academic Publishers, 2001.

4. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd. Surviving the SOC Revolution: A Guide to Platform-Based Designs . Norwell, MA: Kluwer Academic Publishers, July 1999.

5. S. Azimi. Overcoming Challenges and Obstacles to System on Chip (SOC) Products . Sunnyvale, CA: Marvell Semiconductor, Inc., 2000.

6. A. Qureshi (Cadence Design Systems, Inc.). "SOC Design Methodology and Ideal Structures." DesignCon2000.

7. D. Wingard. "Integrating Semiconductor IP Using microNetworks, ASIC Design." Mountain View, CA: Sonics, Inc., 2001.

8. R. Fehr. "Intellectual Property: A Solution for System Design." Technology Leadership Day, October 2000.

9. P. Levin and R. Ludwig. "Crossroads for Mixed-Signal Chips." IEEE Spectrum , March 2002.

10. R. Rajsuman, System-on-a-Chip Design and Test . Santa Clara, CA: Artech House Publishers, 2000.

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