The amount of data that can flow across a bus during a period of time
A1:
Answer: B
2:
Over what system bus are control signals usually sent?
A2:
Answer: Control bus
3:
What is the formula for maximum transfer rate of a bus?
(Speed x Width)/Clock cycles per transfer
(Speed x Clock cycles per bus cycle)/Width
(Width x Clock cycles per bus cycle)/Speed
Speed/(Clock cycles per bus cycle x Width)
A3:
Answer: A
4:
What are four fundamental adjustments that can improve system performance?
A4:
Answer: Any four of the following are acceptable answers:
Increase the speed at which bus cycles take place. This usually means increasing the clock speed of the processor.
Increase the speed at which devices, especially system memory, can communicate with the processor. This involves implementing high-speed memory or adding a cache.
Increase the width of the data bus to increase the amount of information passed in a single bus cycle.
Implement modified bus cycles, such as a burst cycle.
Add concurrent processes, such as dual independent buses or multiprocessing.
5:
What is a bus master device?
A5:
Answer: A device connected to the bus that communicates directly with other devices on the bus without going through the processor.
6:
How many expansion slots operating at 66MHz can a PCI-X bus segment support?
A6:
Answer: Four or more.
7:
How long does PCI-X allow for the decode logic to occur?
A7:
Answer: 7ns
8:
Match the following terms and descriptions:
PCI Express
Incorporates error checking and correcting
PCI-X 2.0
Defines a packetized protocol and a load/store architecture
USB
Enables you to hot plug peripheral devices without restarting or reconfiguring the system
A8:
Answer:
PCI Express: Defines a packetized protocol and a load/store architecture
PCI-X 2.0: Incorporates error checking and correcting
USB: Enables you to hot plug peripheral devices without restarting or reconfiguring the system
