6.5 SHDSL Transceiver Operations
6.5.1 SHDSL PMD LayerThe core technology for SHDSL is based on that of HDSL2, namely, 16-level trellis coded PAM (16TC-PAM). The fundamental difference is that HDSL2 was designed to optimize performance for the transport of 1.544 Mb/s in support of provisioning T1 service on a single wire pair. SHDSL uses 16TC-PAM technology for the provisioning of multirate symmetric services, where the loop distance and noise environment determines the maximum bit rate to be supported on a single wire pair. The payload bit rates defined by SHDSL range from 192 kb/s to 2.312 kb/s in increments of 8 kb/s. The overhead may be either 8 kb/s or 16 kb/s. Generally , the use of 16 kb/s as overhead is a carryover from HDSL. Because SHDSL accommodates all HDSL bit rates in addition to the other bit rates, the same 16 kb/s overhead option was preserved. Figure 6.9 shows the general transceiver block diagram for SHDSL supporting 16-level trellis coded PAM. The upstream and downstream channels share same frequency components , so echo cancellation is the method used to separate the direction upstream and downstream channel transmission. Figure 6.9. General transceiver functional block diagram for HDSL2. The scrambler randomizes the transmit data that is provided by the framer circuit. Randomized data are required for optimal performance of key transceiver algorithms such as the echo canceler and the equalizer. On the receive side, the descrambler provides the reverse operation of the scrambler and feeds the recovered data to the framer. To provide greater immunity to crosstalk and other random background noise, the SHDSL transceiver incorporates trellis coding, which is the same trellis code as used in HDSL2. In the receiver, the trellis decoder is typically implemented, using the Viterbi algorithm to decode the received data, which provides near optimum maximum likelihood estimation of the transmitted symbols. To achieve the benefits of both the trellis coding and decision feedback equalization, channel precoding is applied. The channel precoder basically implements the equivalent of a decision feedback equalizer at the transmitter in which no incorrect symbols are ever transmitted in the feedback filter. This eliminates any error propagation from occurring, which would otherwise degrade performance, and eliminate the effects of the trellis coding gain. The details of the channel precoder are described in detail later in this chapter. The spectral shaper is a high-order low-pass filter that shapes the signal spectrum in a way to provide good performance and assure spectral compatibility with other services in the cable. In SHDSL, there is a family of spectral shapes defined, one for each bit rate. Most of the spectral shapes are symmetric, in that both the upstream and downstream channels share the same spectrum and spectral shape. There are some selected bit rates that have asymmetric shapes defined. These rates are typically the line bit rates defined for classic HDSL, namely,784 kb/s, 1168 kb/s, 1544 kb/s, and 2048 kb/s. Asymmetric power spectral densities (PSDs) have different spectral shapes defined for the upstream and downstream channels. The asymmetric PSDs are specially engineered PSDs to meet a higher performance criteria in support of the service application while maintaining spectral compatibility with other signals in the cable. The analog front-end block contains the digital-to-analog (D/A) conversion, analog filters, and line driver circuits. The hybrid circuit provides the two-to-four wire conversion for connecting the subscriber line to the transmitter output and the receiver input. The receiver front-end block contains analog filters, an automatic gain control circuit that adjusts the total received signal to an optimum level within the circuit's dynamic range, and an analog-to-digital (A/D) converter for converting analog samples into digital samples for processing in the receiver. Because upstream and downstream channels share the same bandwidth, the echo canceler is the device that removes the local echo from the total received signal and passes the desired far-end signal to the receiver for additional processing. The equalizer compensates for any impairment introduced by the channel, such as amplitude and delay distortion. The equalizer is generally an adaptive equalizer, which learns and adapts to the characteristics of the channel during initialization and continuously adapts to any slowing changing line characteristics during data mode. Together with the channel precoder in the transmitter, the two collective algorithms produce the same performance improvements of a decision feedback equalizer (DFE). Because there is no error propagation, the transceiver achieves the performance improvements of both the trellis code and the DFE. Prior to SHDSL, similar services were being provisioned using 2B1Q technology. The functional block diagram of 2B1Q is similar to that of SHDSL in Figure 6.9 except that 2B1Q does not use trellis coding and channel precoding. A bit-to-symbol map is used in place of these two blocks. The performance difference between the two systems is due primarily to the inclusion of a trellis code in SHDSL. The coding gain of the reference trellis code is 5.1 dB. All of the blocks in Figure 6.9, relative to SHDSL, are described in more detail in the following sections. 6.5.2 ScramblerThe SHDSL Recommendation [1] allows for the use of different scrambler polynomials during the different phases of activation, including data mode. Table 6.1 shows a list of the scrambler polynomials of use in G.shdsl. The polynomials used during preactivation are selected during the handshake phase of initialization (see the discussion on initialization later in the chapter). The polynomials of index 0 are generally used in data mode and preactivation mode. The other polynomials are selected for use during the line probe phase of initialization, where the transceivers seek to learn the transmission capability limits of the given line. Figure 6.10 shows a block diagram of the common scrambler structures used in data mode for the downstream and upstream transmitters (index 0), which is the same as those used in HDSL, HDSL2, and ISDN. Figure 6.10. Example SHDSL upstream and downstream channel scrambler. 6.5.3 Trellis EncoderIn order to optimize performance for the different modes, trellis-coded modulation is used to maximize the immunity to crosstalk encountered in the loop plant. This is the same basic trellis code structure used in HDSL2 described in Chapter 4. To minimize the end-to-end latency, any types of block code or concatenated codes that require interleaving were ruled out because the latency introduced was too large. The use of interleaved block codes (such as Reed-Solomon codes), concatenated codes with interleaving, and turbo coding techniques proved to be difficult to use because they require latencies significantly greater than 500 m s to meet the performance objective. What remained was conventional trellis coding with channel precoding (such as the Tomlinson-Harashima precoding). Although multidimensional trellis codes were examined, it was determined that the simple one-dimensional Ungerboeck codes [10] were suitable, meeting up to 5 dB of coding gain (ideal asymptotic coding gain) within a latency of 500 m s. For the one-dimensional Ungerboeck codes, thirty-two states were sufficient to achieve a code gain of 4.0 dB. To achieve 5 dB of coding gain would require implementation of a 512 state code; the challenge here is the design of a decoder such that the implementation loss is minimized and the latency requirement is still met. Two proposals were provided for 512-state trellis codes: one from Pairgain in [11] and the other from Adtran in [12]. Both codes were linear codes claiming coding gains about 5 dB. The commonality is that the two proposed codes used rate one-half convolutional codes where the convolutional coding was performed on one information bit while the other information bits were passed uncoded. The general structure of the trellis is shown in Figure 6.11, where the value of k is 3 (i.e., for every 3 information bits, there are 4 coded output bits. Figure 6.11. HDSL2 trellis encoder structure. Table 6.1. Scrambler Polynomials
To address the numerous codes possible, the agreed trellis code structure includes a programmable non-systematic feed-forward convolutional encoder that codes the least significant bit of the 3-bit information symbol [13]. The structure of the programmable convolutional encoder is shown in Figure 6.12. The convolutional code is a nonsystematic rate one-half code, where for each input data bit there are two output bits. The generator polynomials of the two output paths of the convolutional encoder are Figure 6.12. Convolutional encoder structure. and for outputs Y and Y 1 , respectively. The coefficients a , a 1 , , a 20 and b , b 1 , , b 20 are binary coefficients and the operator '+' represents modulo-2 addition. A reference code having a coding gain of approximately 5 dB has coefficients { a 9 , a 8 , , a } = { 0101101110} and { b 9 , b 8 , , b } = { 1100110001} ; the same coefficients are represented in octal as A = 556 and B = 1461, where all of the digits are octal digits. Another code with approximately the same coding gain has coefficients A = 732 and B = 1063. The entire trellis code in Figure 6.11 is a rate three-fourths code, where the encoder accepts 3 information bits and outputs 4 coded bits. Because the convolutional code that operates on the least significant bit of the input code word is nonsystematic, the trellis code is also nonsystematic. The remaining 2 information bits are passed to the symbol mapper uncoded. The coefficients of the convolutional encoder, defined by two 20th order polynomials, are provided by the manufacturer's equipment that contains the receiver. During initialization, the coefficients are passed from receiver to encoder. An advantage of this programmable approach is that manufacturers could provide codes that are suitable to the type of decoder that they have implemented (e.g., a Viterbi decoder or sequential decoder). Also note that with this configuration, it is possible that the upstream and downstream channel could have different trellis codes. 6.5.4 Bit-to-Symbol MappingThe parallel bits at the output of the trellis encode must be mapped in symbols suitable for transmission on the line. The four bits at the trellis-encoder output are mapped into sixteen possible levels. The bit mapping of each of the levels are shown in Figure 6.13. Figure 6.13. SHDSL bit-to-symbol mapping. The input bits to the trellis encoder are X 1 (m), X 2 (m), and X 3 (m); the output bits are Y 1 (m), Y 2 (m), Y 3 (m), and Y 4 (m). X 1 (m) is the least significant bit of the trellis coder input bits, and Y 1 (m) is the least significant bits of the output symbol. The table in Figure 6.13 shows the mapping of the trellis encoder output bits to the output symbol. The mapping is also shown pictorially in the constellation diagram in the bottom of the figure. 6.5.5 Channel PrecoderThe functional block diagram of the channel pre-coder is shown in Figure 6.14. The receiver computes the feedback filter coefficients ( C 1 , C 2 , , C N ) during the training phase in the initialization process and then transfers the coefficients to transmitter during the parameter exchange phase. The input sequence x ( mT s ) is the output of the bit-to-symbol mapping in the trellis encoder. The output of the feedback filter, n ( mT s ), is computed by Figure 6.14. Channel precoder. where T s is the symbol interval, y ( mT s ) is the precoded output sample, m is the sample time index, and N is number of coefficients in the feedback filter. A modulo-16 operator then operates on the difference between the input sample and feedback filter output sample u ( mT s ). Operation of the modulo-16 block is find an integer d ( mT s ) such that the sum u ( mT s ) + 2 d ( mT s ) falls between the values of “1 and +1. The resulting value of y ( mT s ) is then u ( mT s ) + 2 d ( mT s ). In the HDSL2, the receiver determines the value of N and the value is passed on to the transmitter at initialization during the parameter exchange phase. The value of N has minimum value of 128 and a maximum of 180 samples; any value in between is valid. 6.5.6 Spectral ShaperSHDSL uses a nominal sixth order roll-off filtering of NRZ (nonreturn to zero) pulses . The bandwidth of the main lobe is determined by the symbol rate ( fsym ) of the pulse sequence. The symbol rate is the ratio of the bit rate to the number of information bits per symbol interval, namely, where R b is the bit rate of the line signal and N b is the number of information bits per PAM symbol. For trellis coded 16-level pulse amplitude modulation (PAM), there are three information bits per symbol. The following equation defines the nominal PSDs of SHDSL, which are common for both North America and Europe: where
Table 6.2 summarizes the parameters for the TC-PAM spectral shaper. The parameters in this table are applicable to both North America and Europe. Figure 6.15 shows plots of various SHDSL PSDs for payload bit rates of 256, 384, 512, 768, and 1152 kb/s. These plots do not include the noise floor portion defined in the nominal PSD equation above. The high pass coupling filter is set to 5 kHz, the order of the filter roll-off is 6, and the shaping filter 3 dB cutoff frequency is set to one-half the symbol rate in all cases. Figure 6.15. Nominal PAM PSDs without noise floor. For comparison purposes, Figure 6.16 shows a plot of the 2B1Q SDSL PSDs supporting for the same bit rates as those of the TC-PAM PSDs in Figure 6.15. The 2B1Q signals have 2 information bits per symbol as opposed to 3 information bits for the TC-PAM case; hence, the bandwidth of the TC-PAM spectrum will be narrower (better spectral efficiency) than the equivalent case for 2B1Q configuration. Figure 6.16. Nominal 2B1Q SDSL PSDs without noise floor. 2B1Q SDSL uses fourth order low-pass roll-off as opposed to sixth order roll-off in TC-PAM. As seen in the spectral plots of 2B1Q SDSL in Figure 6.16, the out of band energy is significantly greater for 2B1Q than for TC-PAM. The larger out of band energy is undesirable because of the added crosstalk that would be introduced to other systems in the cable, particularly that into ADSL. In summary, the higher spectral efficiency and higher order filtering of 16-level TC-PAM makes G.shdsl a less disturbing signal to ADSL than 2B1Q SDSL when deployed in the same cable. Upon the adoption of the G.shdsl standard by the ITU-T, 2B1Q SDSL was removed from the basis systems list in the second issue of the spectrum management standard (T1.417) and replaced by G.shdsl (see Chapter 10 for more details on spectrum management). Table 6.2. Parameters for TC-PAM Spectral Shaper
Implementations of PSDs may vary from different manufacturers. The out of band energy may vary depending on the specifics of implementations . To accommodate this variability, the G.shdsl standard [13] defines a noise floor function, which is shown in the nominal PSD equation above. The noise floor is applied at the frequencies above the intercept frequency, which is frequency where the main PSD and noise floor equations intercept in the vicinity of the symbol rate frequency f sym . Figure 6.17 shows plots of the nominal TC-PAM PSDs, which include the out of band noise floor. Actual implementations would have the majority of the out of band PSD below the specified level. Figure 6.17. Nominal PAM PSDs with inclusion of out of band noise floor. In addition to the symmetric PSDs, G.shdsl defines numerous asymmetric PSDs. For North America, the asymmetric PSDs are taken from the HDSL2 standard, and they have been designed for optimal performance and minimal impact on spectral compatibility with other services deployed in the cable. Asymmetric PSDs are defined for 768 or 776 kb/s, and 1536 or 1544 kb/s configurations. | |||||||||||||||||||||||||||||||||||||||||||||||||||
R b 
2,048 kb/s 
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