D.4 Branch Registers

The Itanium architecture defines eight branch registers (Br₀ Br₇), which are 64 bits in width and can thus accommodate full address pointers:

Since Itanium instructions are always fetched three at a time in 128-bit bundles, the lowest four bits of a branch register are always 0. That is, the hexadecimal value of Br_n will always print with the rightmost hex character as 0.

Table D-3 gives the nomenclature and standardized uses of the Itanium branch registers. A register is scratch if it may be freely used by a routine at any calling level (caller must save anything important). A register is preserved if a calling routine depends on its contents (any called procedure must save and restore its contents for its caller).

Table D-3. Itanium Branch Registers

Register	Assembler Name	Other Name	Class	Usage Notes
Br0	b0	rp	Scratch	Return link
Br1 Br5	b1 b5		Preserved
Br6 Br7	b6 b7		Scratch