D.3 Predicate Registers

The Itanium architecture defines 64 predicate registers (Pr₀ Pr₆₃), which are only one bit in width and can thus accommodate only a Boolean true (1) or false (0) value:

Each bit in this 64-bit Pr vector is separately addressable.

Table D-2. Itanium Predicate Registers

Register	Assembler Name	Other Name	Class	Usage Notes
Pr0	p0		Constant	Always 1 (true); writes discarded
Pr1 Pr5	p1 p5		Preserved	Fixed; safe
Pr6 Pr15	p6 p15		Scratch	Fixed; unsafe
Pr16 Pr63	p16 p63	pr.rot	Preserved	Rotating registers

Table D-2 gives the nomenclature and standardized uses of the Itanium predicate registers. A register is constant if its value is permanently defined at the hardware level. A register is scratch if it may be freely used by a routine at any calling level (caller must save anything important). A register is preserved if a calling routine depends on its contents (any called procedure must save and restore its contents for its caller).

Unlike the general register set, no predicate registers are automatically stacked at the time of a procedure call. If necessary, the entire Pr vector can be saved in a general register using the mov pr instruction.