Section 2.4. FPGAs for Parallel Computing

2.4. FPGAs for Parallel Computing

The recent history of high-performance computing research has suggested that massively parallel custom computing engines built of FPGAs (or FPGA-like structures) will play an important role in future applications outside the realm of traditional hardware or embedded systems design. Researchers worldwide have demonstrated that supercomputer-class performance can be obtained for many critical tasks at a tiny fraction of the cost of more general-purpose supercomputing hardware. A common element of the ongoing research in this area is the use of arrays of relatively small, independently synchronized processing elements connected via data streams or messaging-oriented communications. Using this concept of independently synchronized, semi-autonomous processing elements provides great flexibility and power and fits well into an FPGA-based reconfigurable computing approach.

Reconfigurable Computing and the FPGA

Reconfigurable computing is a research area that focuses on carrying out high-performance computations using highly flexible, dynamically reconfigurable computing fabrics such as FPGAs. Reconfigurable computing differs from more traditional computing methods by allowing substantial changes to be made to the data path, in addition to allowing control flow to be altered.

The concept of reconfigurable computing has been around since the 1960s, when a paper published by Gerald Estrin (see Appendix F, "Selected References," for reference) proposed a computer architecture consisting of a standard processor coupled to an array of "restructurable" hardware elements. In such a system, the main processor acted as a controller for the reconfigurable hardware, which was dynamically changed (reconfigured) to perform specific tasks as dedicated hardware. These ideas did not, at the time, lead to a practical implementation, because the underlying capability for dynamic generation of hardware did not yet exist.

Since the introduction of FPGAs in the 1980s, however, there has been a great deal of new research into creating dynamically reconfigurable computers using these relatively low-cost, easy-to-program devices. Multiple conferences are held on this specific topic, including the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), held each spring in Napa, California, and the International Conference on Field-Programmable Logic and Applications (FPL), held in late summer in various European locations.

When it comes to reconfigurable computing, however, FPGAs are not the only story. There have also been newer types of devices, either proposed or actually developed, that lie somewhere between FPGAs and standard processors. These coarse-grained programmable devices promise both the hardware flexibility of FPGAs and the software programmability of traditional processors, with less overhead in terms of the on-chip interconnects and related place-an d-route issues mentioned earlier. As of this writing, however, none of these new architectures (which in the commercial sector have been offered by companies including PACT, IPFlex, Quicksilver, Morphics, Chameleon, picoChip, and others) have proven to be general-purpose enough to become true microprocessor alternatives. Perhaps equally important, no unifying programming methodology has yet emerged for highly parallel, hardware-based computing. Such a common methodology is important to allow this new technologyreconfigurable computingto become widely popular.