2.3. Systems on a Programmable Chip
Embedded (or "soft") IP cores representing common, low-complexity microprocessors and microcontrollers have been available from third-party suppliers (typically subject to a licensing fee, although free, open-source cores are also available) for well over a decade. Using such cores in combination with other related peripheral cores makes it possible to create complete systems composed of, for example, an 8- or 16-bit controller, a UART, and other such I/O devices on a single programmable chip. It has become quite common, in fact, for embedded systems designers to forgo the use of dedicated legacy controllers (such as Zilog Z-80s, Intel 8051s, PIC processors, and others) and instead implement these processors directly within programmable hardware. This has had obvious revenue implications for the original processor developers and suppliers, who often have no IP protection apart from copyrightedand easily replacedassembly language specifications.
More recently, major FPGA vendors have created proprietary 32-bit processor cores optimized for their own FPGA devices and have made these processor cores available to their users at a very low cost, typically a few thousand dollars for a development license with no per-unit royalties. Both Xilinx and Altera have also created hybrid processor/FPGA platforms that combine standard 32-bit processors (a PowerPC and an ARM, respectively) with general-purpose programmable FPGA fabric to create what are often referred to as "platform FPGAs."
As FPGA densities increased, it became clear that the types of systems that could be implemented in this way were truly without bounds. One limiting factor in the general acceptance of FPGA-based systems-on-chip, however, has been on-chip interface standards. Combining IP cores from multiple vendors has proven to be a challenge, and here again the FPGA vendors have offered solutions that advance the usefulness of their proprietary platforms. Altera, for example, promotes the use of its Avalon interconnect and the related SOPC Builder software tools as a way to greatly simplify the selection and interconnection of a growing number of Altera and third-party IP cores. Xilinx, with its Platform Studio software and OPB bus, provides similar capabilities. In the open-source IP community, the Wishbone standard (originally developed by Wade Peterson of Silicore, Inc.) has gained converts.
The ability to quickly assemble a programmable hardware platform that combines one or more customized embedded processors with other third-party IP cores and general-purpose programmable logic resources is a great enabler for high-performance embedded applications. For embedded systems designers, then, all that is missing is a way to create new hardware functions and integrate them cleanly with other IP coreswithout requiring hardware design skills. This is, of course, where software-to-hardware compiler tools are beginning to play a role.
Toward Faster System Prototypes and Higher Performance
Fundamentally, an FPGA provides the opportunity to create arbitrary hardware structures and to connect these structures using a switched fabric of programmable interconnects. The flexibility of such a platform creates enormous opportunities for increasing the performance of algorithmsin particular, algorithms that can make use of parallelism. Without an efficient and semi-automated way to compile higher-level algorithms to equivalent lower-level hardware structures, however, the rapid creation of high-performance systems is difficult to achieve.
A software-to-hardware compiler that allows applications (or application components) to be compiled directly to an FPGA is a critical component of a rapid prototyping environment. By introducing C-language compilation to an existing design flow, it becomes possible to more quickly experiment with alternative design concepts and to create working prototypes. And by using the same design entry language and software-oriented methods of debugging and verification, system designers can very quickly create and evaluate different prospective hardware and software partitioning strategies and create working product prototypes. As C-to-hardware tools mature and FPGAs become larger, using such methods of design (whether the input language is C or some other language more appropriate for parallel programming), the practicality of hand-coding large applications at the level of HDLs will diminish to the point where such methods will be used for only the most performance-critical and/or irregular types of hardware components.