Single-Ended Signaling Characteristics

The single-ended signals must be routed to the link interface(s) of all devices. The specification states that routing "must be done in a daisy-chain fashion, with any stubs being less than 1 inch in length." The general characteristics of each of the single-ended signals are also the same:

• Output drivers must be implemented as Open Drain LVCMOS

• A pullup resistor ( 1K ) is required to support the open drain drivers.

• Receivers must be implemented as single-ended 2.5V Tolerant LVCMOS

RESET# and PWROK may be implemented as input-only, depending on whether the device has been designed to extend RESET# during initialization. Table 14-10 lists the power requirements, input and output voltages, current requirements and edge rates that are specified for compliant operation.

Table 14-10. Single-Ended Signaling Characteristics

Symbol	Parameter	Test Conditions		Min	Typ	Max	Unit
V DD	Supply Voltage			2.37	2.5	2.63	V
V IH	Input Voltage (high)	V OUT V VOH (min)		1.7		VDD+0.3	V
V IL	Input Voltage(low)	V OUT V VOL (max)		-0.3			V
Tr	Input Rise Time	V il < V in < V ih monotonic		0.01			V/ns
Tf	Input Fall Time	V ih > V in > V il non-monotonic		0.01			V/ns
V OL	Output Voltage(low)	V DD = min, V I = V IH or V IL	I OL = 2mA			0.7	V
I I		V DD = max, V I = V DD or GND				±500	m A