6.3 100BaseT4

All versions of Ethernet with a transmission throughput of 100 Mbps belong to the group of 100BaseT. They include 100BaseT4 on four pairs of a Category 3 or better twisted pair cable, 100BaseTX on two pairs of a Category 5 twisted pair cable, 100BaseFX on two multimode fibers, and 100BaseT2 on two pairs of a Category 3 or better twisted pair cable. All twisted pair based 100BaseT Ethernet will be discussed in the remainder of this chapter. All these twisted pair based Ethernet versions use the same RJ-45 connector. To recognize each Ethernet transceiver's physical layer capabilities and to obtain the best performance match between multimode transceivers, an autonegotiation process, which will be discussed at the end of this chapter, is normally used at the beginning of each transmission session. On the other hand, a Media Independent Interface between different physical layers and the common MAC layer is also defined as a part of the Ethernet standard.

All four twisted pairs of a Category 3 cable are occupied by 100BaseT4. Among these four pairs, one is always used for transmitting, another one is always used for receiving, and the remaining two are used for either activity, depending on the data traffic direction. The 100-Mbps transmission throughput is equally divided among three transmitting pairs. Each byte (8 bits) group of binary information bits on one twisted pair is further converted into a group of six ternary symbols of three possible values: 1, 0, and +1. The symbol baud rate on each twisted pair is therefore 100/3 x 6/8 = 25 MHz. The always transmitting pair is connected to pin #1 and pin #2 and the always receiving pair is connected to pin #3 and pin #6 on an RJ-45 connector for a 100BaseT4 NIC as shown in Figure 6.24. These transmitting and receiving pair pin positions are consistent with those of 10BaseT; therefore, the autonegotiation procedure can be carried out without signaling conflict. Two 100BaseT4 NICs can also be connected directly with a crossover cable as defined in Figure 6.25.

Figure 6.24. Internal Crossover (From IEEE Std. 802.3. Copyright © 2000 IEEE. All rights reserved.)

Figure 6.25. External Crossover (From IEEE Std. 802.3. Copyright © 2000 IEEE. All rights reserved.)

6.3.1 Summary of the 100BaseT4 Ethernet Standards

The transmission characteristics of a 100-m Category 3 twisted pair for the 100BaseT4 Ethernet application is redefined in terms of a differential circuit model. The topology and component values of this transmission media model are shown in Figure 6.26. The insertion loss of this differential model can also be calculated through proper ABCD matrices manipulation. Each section of this model can be grouped into five two-port networks with corresponding ABCD matrices. These five two-port networks for the first section are shown in Figure 6.27. This section can be considered as three two-port networks, N₁, N₂, and N₃ in parallel. N₃ can be further divided into three two-port networks N₃₁, N₃₂, and N₃₃ in series. The ABCD matrix for a two-port network with impedances Z₁, as R₈ of N₁, in the top path and Z₂, as R₃₄ of N₁, in the bottom path is

Equation 6.13

Figure 6.26. Differential Channel Model (From IEEE Std. 802.3. Copyright © 2000 IEEE. All rights reserved.)

Figure 6.27. Two-Port Network Equivalence

Figure 6.28 shows insertion loss of the differential model in comparison with that specified for 10BaseT. For this differential model, insertion losses are about 10 and 15 dB at frequencies of 10 and 20 MHz, respectively. The insertion loss defined by this differential circuit model is closer to that of the propagation model, while the cable model for 10BaseT is closer to a particular measurement.

Figure 6.28. Insertion Loss

Based on the differential circuit model and its ABCD matrices representations, the insertion loss can be described by a fraction polynomial in complex frequency, s, domain as follows. We will use this model in later Simulink simulation for the convenience of sampling rate independence.

Equation 6.14

NEXT models are defined as 24.5 and 21.4 dB at 12.5 MHz for single- and multiple-pair disturbers by Equations 6.15 and 6.16, respectively.

Equation 6.15

Equation 6.16

The 15-dB/decade three-pair crosstalk model with a loss of 21.4 dB at 12.5 MHz is approximated with an RLC network using the basic sectional structure of the circuit channel model. Figure 6.29 shows the insertion loss of this RLC network as well as that of the 15-dB/decade model. Loss differences are less than 0.5 dB in the frequency range of 1 30 MHz. This circuit multiple pair NEXT model can also be described by a fractional polynomial in complex frequency, s, domain as

Equation 6.17

Figure 6.29. Crosstalk Loss

The mapping between a byte and a group of six ternary symbols is specified in the Appendix of the IEEE standard and is repeated in Table 6.3 here for convenience. It is worth noting that the coding table is not zero balanced because there is a positive bias if you add all ternary groups together. To be exact, there are 122 ternary groups of symbols with 1 net positive pulse when positive and negative pulses within a symbol are compared. The DC balance on the twisted pair is maintained by the DC balance algorithm built into the transmitter. A bit is reserved to monitor the accumulation of DC balance. The bit is set to zero at the beginning. If the bit is zero while a positive biased ternary group is encountered, the bit is set to 1, and the ternary code is transmitted. However, if the bit is one when a positive biased ternary group is encountered, the bit is reset to zero, and every ternary symbol of this group is negated and then transmitted. The negated group of ternary symbols can be revised in the receiver since only groups of ternary symbols with zero or positive bias are defined.

Normalized transmit pulse masks are defined in the standards for two examples of a zero-separated positive and negative pulse sequence and an adjacent positive and negative pulse sequence as shown by Figures 6.30 and 6.31. In Figure 6.30, the positive and negative pulses are separated by five zeros. Each pulse can be formulated with a 100% excessive bandwidth raised cosine filter followed by a third-order low-pass Butterworth filter with a corner frequency of 25 MHz. Figure 6.32 shows the PSD of the 100BaseT4 signal with filters in comparison with that formed by rectangle pulses. These filters significantly reduce the energy level at above 25 MHz.

Figure 6.30. Positive and Negative Pulses Separated by Zeros (From IEEE Std. 802.3. Copyright © 2000 IEEE. All rights reserved.)

Figure 6.31. Adjacent Positive and Negative Pulses (From IEEE Std. 802.3. Copyright © 2000 IEEE. All rights reserved.)

Figure 6.32. 100BaseT4 PSD

Table 6.3. 8B6T Encoding

00	+-00+-	2B	0--+0+	56	+0++--	81	++-0-0	AC	+--++-	D7	-+++0-
01	0+-+-0	2C	0--++0	57	0+++--	82	+-+0-0	AD	--+-++	D8	0+00-+
02	+-0+-0	2D	--00++	58	+++0--	83	-++0-0	AE	-+--++	D9	00+-+0
03	-0++-0	2E	-0-0++	59	+++-0-	84	-++00-	AF	+---++	DA	0+0-+0
04	-0+0+-	2F	0--0++	5A	+++--0	85	++--00	B0	0-000+	DB	+00-+0
05	0+--0+	30	+-00-+	5B	++0--0	86	+-+-00	B1	00-0+0	DC	+000-+
06	+-0-0+	31	0+--+0	5C	++0--+	87	-++-00	B2	0-00+0	DD	00++0-
07	-0+-0+	32	+-0-+0	5D	++000-	88	0+000-	B3	-000+0	DE	0+0+0-
08	-+00+-	33	-0+-+0	5E	--+++0	89	00+0-0	B4	-0000+	DF	+00+0-
09	0-++-0	34	-0+0-+	5F	00-++0	8A	0+00-0	B5	00-+00	E0	+-0++-
0A	-+0+-0	35	0+-+0-	60	0-0++0	8B	+000-0	B6	0-0+00	E1	0+-+-+
0B	+0-+-0	36	+-0+0-	61	00-+0+	8C	+0000-	B7	-00+00	E2	+-0+-+
0C	+0-0+-	37	-0++0-	62	0-0+0+	8D	00+-00	B8	-+-00+	E3	-0++-+
0D	0-+-0+	38	-+00-+	63	-00+0+	8E	0+0-00	B9	--+0+0	E4	-0+++-
0E	-+0-0+	39	0-+-+0	64	-00++0	8F	+00-00	BA	-+-0+0	E5	0+--++
0F	+0--0+	3A	-+0-+0	65	00-0++	90	+-+--+	BB	+--0+0	E6	+-0-++
10	+0+--0	3B	+0--+0	66	0-00++	91	++--+-	BC	+--00+	E7	-0+-++
11	++0-0-	3C	+0-0-+	67	-000++	92	+-+-+-	BD	--++00	E8	-+0++-
12	+0+-0-	3D	0-++0-	68	-+-++0	93	-++-+-	BE	-+-+00	E9	0-++-+
13	0++-0-	3E	-+0+0-	69	--++0+	94	-++--+	BF	+--+00	EA	-+0+-+
14	0++--0	3F	+0-+0-	6A	-+-+0+	95	++-+--	C0	+-+0+-	EB	+0-+-+
15	++00--	40	+0+00-	6B	+--+0+	96	+-++--	C1	++-+-0	EC	+0-++-
16	+0+0--	41	++00-0	6C	+--++0	97	-+++--	C2	+-++-0	ED	0-+-++
17	0++0--	42	+0+0-0	6D	--+0++	98	0+0--+	C3	-+++-0	EE	-+0-++
18	0+-0+-	43	0++0-0	6E	-+-0++	99	00+-+-	C4	-++0+-	EF	+0--++
19	0+-0-+	44	0++00-	6F	+--0++	9A	0+0-+-	C5	++--0+	F0	+-000+
1A	0+-++-	45	++0-00	70	-++000	9B	+00-+-	C6	+-+-0+	F1	0+-0+0
1B	0+-00+	46	+0+-00	71	+-+000	9C	+00--+	C7	-++-0+	F2	+-00+0
1C	0-+00+	47	0++-00	72	++-000	9D	00++--	C8	0+00+-	F3	-0+0+0
1D	0-+++-	48	000+00	73	00+000	9E	0+0+--	C9	00++-0	F4	-0+00+
1E	0-+0-+	49	000-++	74	-0+000	9F	+00+--	CA	0+0+-0	F5	0+-+00
1F	0-+0+-	4A	000+-+	75	0-+000	A0	0-0++-	CB	+00+-0	F6	+-0+00
20	00-++-	4B	000++-	76	+0-000	A1	00-+-+	CC	+000+-	F7	-0++00
21	--+00+	4C	000-+0	77	0+-000	A2	0-0+-+	CD	00+-0+	F8	-+000+
22	++-0+-	4D	000-0+	78	0--+++	A3	-00+-+	CE	0+0-0+	F9	0-+0+0
23	++-0-+	4E	000+-0	79	-0-+++	A4	-00++-	CF	+00-0+	FA	-+00+0
24	00+0-+	4F	000+0-	7A	--0+++	A5	00--++	D0	+-+0-+	FB	+0-0+0
25	00+0+-	50	+0+--+	7B	--0++0	A6	0-0-++	D1	++--+0	FC	+0-00+
26	00-00+	51	++0-+-	7C	++-00-	A7	-00-++	D2	+-+-+0	FD	0-++00
27	--+++-	52	+0+-+-	7D	00+00-	A8	-+-++-	D3	-++-+0	FE	-+0+00
28	-0-++0	53	0++-+-	7E	++---+	A9	--++-+	D4	-++0-+	FF	+0-+00
29	--0+0+	54	0++--+	7F	00+--+	AA	-+-+-+	D5	++-+0-
2A	-0-+0+	55	++0+--	80	+-+00-	AB	+--+-+	D6	+-++0-

Data nibbles (4 bits) from the MII interface are recombined into three sequences of bytes and evenly distributed among three twisted pairs for transmission according to frame structures as shown in Figure 6.33. Preambles are initiated after data nibbles become available and are inserted before data ternary symbols. Depending on a particularly identified twisted pair, a preamble contains a combination of groups of P3, P4, SOSA, or SOSB ternary symbols. P3 consists of a pair of adjacent positive and negative ternary pulses. P4 consists of two adjacent P3s for a total of four ternary pulses. SOSA is a sequence of three P3s for a total of six ternary pulses. SOSB consists of a P4 followed by a negated P3 also for a total of six ternary symbols. At the transmitter side, data ternary symbols appear on the BI_D4 twisted pair first, on the TX_D1 pair next, and on the BI_D3 pair last. Data symbol group latencies are two ternary symbols apart from one pair to the next. The preamble on the BI_D4 pair consists of a P4, a SOSA, and a SOSB in sequence and lasts 16 ternary symbols. The preamble on the TX_D1 pair consists of two SOSAs and one SOSB and lasts 18 ternary symbols. The preamble on the BI_D3 pair consists of a P3, two SOSAs, and a SOSB in sequence and lasts 20 ternary symbols.

Figure 6.33. 100BaseT4 Frame Structures (From IEEE Std. 802.3. Copyright © 2000 IEEE. All rights reserved.)

Groups of End of Packets (EOP) ternary symbols are appended at the end of data ternary symbols at each of these three transmitting twisted pairs. The pair with the last group of data ternary symbols is appended with an EOP_3 consisting of two positive ternary symbols followed by two negative ternary symbols (and followed by two zeros) or [+1 +1 1 1 0 0]. The pair with the next-to-the-last group of data ternary symbols is appended with EOP_2 ([+1 +1 +1 +1 1 1]) and EOP_5 ([ 1 1 0 0 0 0]). The remaining pair is appended with EOP_1 ([+1 +1 +1 +1 +1 +1]) and EOP_4 ([ 1 1 1 1 1 1]). The last group of data ternary symbols could be at any of these three transmitting twisted pairs depending on the length of data from MII.

6.3.2 100BaseT4 Transceiver Structure and Performance Estimation

A possible 100BaseT4 transceiver structure is shown in Figure 6.34. The transmit part consists of three transmitters of similar functionalities. Data are separated one byte at a time and equally distributed among these three transmitters. Each transmitter has its own framing, 8B6T encoding, and shaping functions. Similarly, the receive part also consists of three receivers for corresponding twisted pairs. Each receiver has its own equalization, three-level decision, 8B6T decoding, and deframing functions. The recovered data are then combined byte by byte for external consumption. A phase-locked loop is also used inside the receive part for timing recovery.

Figure 6.34. 100BaseT4 Transceiver Structure

The theoretical performance of a 100BaseT4 transceiver under the worst case NEXT environment as defined by the standards can be analyzed by comparing the SNR at the front of the receiver. Figure 6.35 shows receiver front-end signal and crosstalk PSDs for a frequency band of 0 to 25 MHz. The R-, L-, and C-based differential channel and the multidisturber crosstalk models are used to generate these PSDs, respectively. The corresponding SNR is shown in Figure 6.36.

Figure 6.35. Received Signal and Crosstalk Noise PSD

Figure 6.36. Receiver Front-End SNR

Based on these receiver front-end SNRs, the channel capacity for the 100BaseT4 transmission environment is found using

Equation 6.18

At about 108 Mbps, the channel capacity is about 3.3 times the throughput of the 100BaseT4 transmission protocol.

Computer simulation can be used to study the performance of a typical 100BaseT4 transmission system under different channel and noise environments. Figure 6.37 shows a 100BaseT4 Simulink model block diagram at its highest hierarchical level. This Simulink model consists of a random binary sequence generator as the signal source, a 100BaseT4 transmitter to convert the information sequence into 8B6T encoded line voltage on the twisted pair cable, another pair of binary sequence generator and transmitter as the crosstalk source, a four-pair Category 3 channel model, and a 100BaseT4 receiver. Four scopes are placed right after the information sequence, the transmitter, the channel, and the receiver to collect simulation results.

Figure 6.37. 100BaseT4 Simulink Model

Figure 6.38 shows the internal structure of the Simulink model transmitter. The data are separated byte-by-byte into three streams. The separated data stream is passed through an 8B6T encoder consisting of a lookup translation table. The line voltage is produced by driving the combination of a 100% excessive bandwidth raised cosine and a third-order Butterworth low-pass filter with these ternary symbols.

Figure 6.38. 100BaseT4 Transmitter Simulink Model

Figure 6.39 shows the internal structure of the Simulink model receiver. The received data are first passed through a fixed or an adaptive channel equalizer. A phase-locked loop is used to recover the timing information. The equalized signal is then sampled based on the recovered clock and quantized into three levels. The 8B6T decoder part is similar to that of the transmitter and is not implemented in this Simulink model for simplicity.

Figure 6.39. 100BaseT4 Receiver Simulink Model

According to this Simulink simulation, an equalizer, at least a fixed one, is necessary for an 100BaseT4 receiver to recover data from the received signal. Figure 6.40 shows the eye diagram right after the Simulink 100BaseT4 transmitter. Without using a channel equalizer, the eye is completely closed after the Category 3 twisted pair channel model. Figure 6.41 shows the eye diagram after the simple fixed equalizer inside the Simulink 100BaseT4 receiver. This simple fixed-channel equalizer can be implemented with two resistors and a capacitor as shown in Figure 6.42. The transfer function of this simple fixed equalizer is expressed as

Equation 6.19

Figure 6.40. Eye Diagram at the Transmitter

Figure 6.41. Eye Diagram at the Receiver with an Equalizer

Figure 6.42. The Implementation of the Fixed Equalizer

A fixed compromise equalizer to accommodate different lengths of twisted pair cables or an adaptive analog channel equalizer can be defined to achieve a better data detection performance.