Part of code development is dealing with exceptions. In Chapter 2,"Coding Standards," aligning memory and using assertions were the primary topics. Using misaligned memory with an instruction that requires alignment will generate an exception. The floating-point chapter (Chapter 8) mentioned how a divide by zero or square root of N should be avoided. Exceptions are in reality interrupts that vector the processor to special handling code when a situation occurs, but despite being an interrupt it is directly related to debugging an application and so they are being discussed here instead of Chapter 10, "Branching." Let us examine this a bit closer.
There are two types of exceptions in the 80x86 processor: hardware and software. The hardware exception has a maskable and non-maskable type. The software exception has three subtypes : fault, trap, and abort.
Nonmaskable Signaled by a NMI (nonmaskable interrupt) and cannot be ignored.
Maskable Signaled by a INTR but can be ignored by clearing the Interrupt flag in EFLAGS with the instruction CLI.
Fault A detectable error before it occurs, but the program is restartable.
Trap An error is trapped after it occurs, but the application is not restartable.
Abort An error trapped after it occurs, but the program may need to be terminated .
Almost every instruction that the 80x86 uses has an association with an exception. Some have been mentioned, but if they had been thoroughly documented this book would be at least twice its size . So general rules apply, such as the divide by zero, using privileged instructions from a non-privileged protection layer, trying to use bad floating-point values, protection violations, and internal machine faults. Even a breakpoint that is set and triggered during debugging is an exception. Each exception is indicated by a "#" followed by a two-letter ID encapsulating an optional error code in parentheses: #GP(fault#). For example, #GP(0) is a general-protection fault with an error code of zero. The following is a list of exceptions.
When an exception occurs, an interrupt is generated and the instruction pointer is immediately redirected to the special handler associated with the interrupt slot in the Interrupt Descriptor Table (IDT). Each slot in the table is a gate to layer #0. As shown in Table 21-1, there are up to 256 interrupts, of which 32 are reserved for exceptions and interrupts. Note that some are actually unused and reserved for the future.
#DE 0 Divide by zero. DIV and iDIV
#DB Debug (reserved for Intel use only)
NMI (non-maskable interrupt)
#BP Breakpoint. INT 3
#OF Overflow. INTO
#BR Bound. BOUND
#UD Invalid opcode. UD2 or reserved
#NM Device n/a. FPU, WAIT/FWAIT
Windows Assembly Language and Systems Programming: 16- and 32-Bit Low-Level Programming for the PC and Windows