Memory access instructions

Unlike some other instruction sets, the SPARC Version 8 instruction set never embeds memory addresses into the instructions. Thus, no instructions can directly modify the contents of memory. Instead, all data manipulation is performed in the SPARC general purpose registers.

Two basic memory access operations can be performed on SPARC systems. These are "load" and "store" or, in other words, "read from memory" and "write to memory." There are several variations of these two operations which handle different data sizes.

Using load instructions, data is read in from memory and stored into a register. Once in a register, the data can be manipulated as needed. Using store instructions, the modified data is written back to memory.

Load instructions

The load instruction is used to read a value stored in memory, placing the data into a register when it can then be manipulated. Here are six commonly used load instructions:

Table B-1. SPARC load instructions

Instruction Syntax	Operation
ld [ address ], reg	Read word from memory (address) and load into register
ldd [ address ], reg	Read double word and load into register and next register
ldsb [ address ], reg	Read signed byte from memory and load into register
ldsh [ address ], reg	Read signed half-word and load into register
ldub [ address ], reg	Read unsigned byte and load into register
lduh [ address ], reg	Read unsigned half-word and load into register

Now let's look at a couple of examples. The instruction below reads the word of data stored at the memory address indicated by input register %i0 and loads it into output register %o1 .

 ld [%i0], %o1 

The next example reads an unsigned byte of data from memory, loading it into output register %o3 . The memory address where the byte is read is the contents of input register %i4 plus hexadecimal 8. In a case like this, the value in %i4 may often be the pointer to a structure. The offset of 8 points to the most significant byte of the third word in the structure, the 9th byte.

 ldub [%i4 + 0x8], %o3 

The example below reads a double word (two words) from memory and loads the data into two registers starting with register %l4 . So, if %i3 contains address 0xfea603b0, this load instruction will read memory location 0xfea603b0 and 0xfea603b4, loading the data into registers %l4 and %l5 , respectively.

 ldd [%i3], %l4 

Loading from alternate address space

Each of the six load instructions shown above also has a variation that says to load the information from an alternate address space, such as the control registers for the Memory Management Unit. Each SPARC implementation may offer different alternate addressable registers that can be accessed via the load alternate address space instructions. During system crash dump analysis, odds are very good you will not run into these instructions, since they are not generated by the compiler, but we'll show them just in case you do encounter them. Here they are.

Table B-2. Load instructions from alternate address space

Instruction Syntax	Operation
lda [ reg ] asi, reg	Load word from alternate space
ldda [ reg ] asi, reg	Load double word from alternate space
ldsba [ reg ] asi, reg	Load signed byte from alternate space
ldsha [ reg ] asi, reg	Load signed half-word from alternate space
lduba [ reg ] asi, reg	Load unsigned byte from alternate space
lduha [ reg ] asi, reg	Load unsigned half-word from alternate space

Loading from the floating-point unit & coprocessor

The next six load instructions are specifically for the optional floating-point unit and the optional coprocessor. While in assembly language they appear to be instructions we've seen earlier, the actual opcodes differ .

Table B-3. Load instructions for optional FPU

Opcode	Instruction Syntax	Operation
LDF	ld [ address ], freg	Load word from memory into freg
LDDF	ldd [ address ], freg	Load double word from memory into freg
LDFSR	ld [ address ], %fsr	Load word into floating-point state reg
LDC	ld [ address ], creg	Load word from memory into creg
LDDC	ldd [ address ], creg	Load double word from memory into creg
LDCSR	ld [ address ], %csr	Load word into coprocessor state register

Store instructions

If you feel comfortable with the various load instructions, the store instructions will be a piece of cake. After data in a register has been manipulated, we use the store instruction to write the data to a specified memory location.

There are four basic store operations and four alternate address space variations of them. They are as follows :

Table B-4. SPARC store instructions

Instruction Syntax	Operation
stb reg , [ address ]	Store least significant byte to memory (aka stub and stsb )
sth reg , [ address ]	Store least significant half-word (aka stuh and stsh )
st reg , [ address ]	Store word to memory
std reg , [ address ]	Store double word to memory
stba reg , [ regaddr ] asi	Store byte to alternate space (aka stuba and stsba )
stha reg , [ address ] asi	Store half-word to alternate space (aka stuha and stsha )
sta reg , [ address ] asi	Store word to alternate space
stda reg , [ address ] asi	Store double word to alternate space

Let's take a look at a couple of examples of store instructions. The one below stores the contents of input register %i3 into the memory location whose address is in local register %l6 .

 st %i3, [%l6] 

The next example stores the least significant byte in register %i0 into the 2nd byte of the word whose address is contained in register %l5 .

 stb %i0, [%l5 + 1] 

Storing from the floating-point unit & coprocessor

Of course, we also have additional store instructions that are used in conjunction with the optional floating-point processor and optional coprocessor. As with the load instructions, these instructions differ a bit between assembly language and the actual SPARC opcode.

Table B-5. SPARC additional store instructions

Opcode	Instruction Syntax	Operation
STF	st freg , [ address ]	Store word in freg to memory
STDF	std freg , [ address ]	Store double word in freg to memory
STFSR	st %fsr, [ address ]	Store %fsr to memory
STDFQ	st %fq, [ address ]	Store double %fq to memory
STC	st creg , [ address ]	Store word in creg to memory
STDC	std creg , [ address ]	Store double word in creg to memory
STCSR	st %csr, [ address ]	Store %csr to memory
STDQC	std %cq, [ address ]	Store double %cq to memory

Atomic memory access instructions

Two instructions in the SPARC instruction set and two alternate address space variations of them can perform a read from memory and a write to memory atomically.

What do we mean by atomically? The instruction cannot be interrupted during its execution; the read and the write happen in the same breath . In a multiprocessor system, two or more processors executing the instructions addressing the same byte simultaneously are guaranteed to execute them in an undefined, but serial order.

Here are the instructions:

Table B-6. SPARC atomic energy access instructions

Instruction Syntax	Operation
ldstub [ address ] , reg	Atomic load-store unsigned byte
ldstuba [ regaddr ] asi, reg	Atomic load-store unsigned byte into alternate space
swap [ address ] , reg	Swap register with memory
swapa [ regaddr ] asi, reg	Swap register with alternate space memory

The ldstub instructions read an unsigned byte from memory into a register, then write all ones (hexadecimal 0xff) to that byte of memory. The swap instructions interchange the contents of a memory location with the contents of a register.

In general terms, both of these instructions, since they involve a lot of work, usually take longer to execute than others. However, when integrity of the data being manipulated is critical and timing is everything, these atomic instructions are invaluable. For example, it is the ldstub instruction that provides SPARC systems the ability to have safe, predictable locking mechanisms.

Note

Instruction execution times differ with each SPARC implementation. Refer to the specific processor's technical manual for timing data.

Possible traps during memory access instructions

The memory access instructions generate the most traps. With the exception of the floating-point and coprocessor trap conditions, the traps shown below will cause a user program to terminate, dumping core . When these conditions are detected during execution of kernel code, it is considered catastrophic, and the system will immediately panic with a "bad trap.".

Table B-7. SPARC trap conditions and causes

Trap Condition	How The Condition Is Caused
Illegal instruction	The operation code of the instruction being executed did not represent a valid instruction.
Privileged instruction	The processor is not in privileged mode and the instruction being executed is a privileged instruction. Alternate address space instructions, stdfq and stdcq are all privileged instructions and will cause this when PSR bit S is 0.
Memory address not aligned	A double word, full word or half-word instruction is trying to access memory that is not double word, full word or half-word aligned. Byte instructions cannot cause this condition.
Data access exception	Failure to access the data due to a condition such as the page of memory being marked as invalid or write-protected.
Data access error	The instruction failed to complete access of the data due to a condition such as a data cache parity error or an uncorrectable ECC memory error.
Data store error	The instruction failed to complete storage of the data due to a condition such as a bus parity error.
FP / CP disabled	Attempt to access the floating-point processor (or coprocessor) that is not present or while PSR EF (or EC) bit is set to 0.
FP / CP exception	A floating-point (or coprocessor) instruction generated an exception.

When analyzing a system crash dump caused by a "bad trap," you'll usually find that a load or store instruction caused the crash.